Esempio n. 1
0
static void amd8111_lpc_bridge_check(struct edac_device_ctl_info *edac_dev)
{
	struct amd8111_dev_info *dev_info = edac_dev->pvt_info;
	struct pci_dev *dev = dev_info->dev;
	u8 val8;

	edac_pci_read_byte(dev, REG_IO_CTRL_1, &val8);
	if (val8 & IO_CTRL_1_CLEAR_MASK) {
		printk(KERN_INFO
			"Error(s) in IO control register on %s device\n",
			dev_info->ctl_name);
		printk(KERN_INFO "LPC ERR: %d, PW2LPC: %d\n",
			(val8 & IO_CTRL_1_LPC_ERR) != 0,
			(val8 & IO_CTRL_1_PW2LPC) != 0);

		val8 |= IO_CTRL_1_CLEAR_MASK;
		edac_pci_write_byte(dev, REG_IO_CTRL_1, val8);

		edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
	}

	if (at_compat_reg_broken == 0) {
		u8 out8 = 0;
		val8 = __do_inb(REG_AT_COMPAT);
		if (val8 & AT_COMPAT_SERR)
			out8 = AT_COMPAT_CLRSERR;
		if (val8 & AT_COMPAT_IOCHK)
			out8 |= AT_COMPAT_CLRIOCHK;
		if (out8 > 0) {
			__do_outb(out8, REG_AT_COMPAT);
			edac_device_handle_ue(edac_dev, 0, 0,
						edac_dev->ctl_name);
		}
	}
}
Esempio n. 2
0
static int
dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)
{
	struct llcc_drv_data *drv = edev_ctl->pvt_info;
	int ret;

	ret = dump_syn_reg_values(drv, bank, err_type);
	if (ret)
		return ret;

	switch (err_type) {
	case LLCC_DRAM_CE:
		edac_device_handle_ce(edev_ctl, 0, bank,
				      "LLCC Data RAM correctable Error");
		break;
	case LLCC_DRAM_UE:
		edac_device_handle_ue(edev_ctl, 0, bank,
				      "LLCC Data RAM uncorrectable Error");
		break;
	case LLCC_TRAM_CE:
		edac_device_handle_ce(edev_ctl, 0, bank,
				      "LLCC Tag RAM correctable Error");
		break;
	case LLCC_TRAM_UE:
		edac_device_handle_ue(edev_ctl, 0, bank,
				      "LLCC Tag RAM uncorrectable Error");
		break;
	default:
		ret = -EINVAL;
		edac_printk(KERN_CRIT, EDAC_LLCC, "Unexpected error type: %d\n",
			    err_type);
	}

	return ret;
}
Esempio n. 3
0
static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
{
	struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
	u32 err_detect;

	err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);

	if (!(err_detect & L2_EDE_MASK))
		return;

	printk(KERN_ERR "ECC Error in CPU L2 cache\n");
	printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
	printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
	       in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
	printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
	       in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
	printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
	       in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
	printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
	       in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
	printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
	       in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));

	/* clear error detect register */
	out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);

	if (err_detect & L2_EDE_CE_MASK)
		edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);

	if (err_detect & L2_EDE_UE_MASK)
		edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
}
Esempio n. 4
0
/**
 * zynqmp_ocm_edac_handle_error - Handle controller error types CE and UE
 * @dci:	Pointer to the edac device controller instance
 * @p:		Pointer to the ocm ecc status structure
 *
 * Handles the controller ECC correctable and un correctable error.
 */
static void zynqmp_ocm_edac_handle_error(struct edac_device_ctl_info *dci,
				    struct zynqmp_ocm_ecc_status *p)
{
	struct zynqmp_ocm_edac_priv *priv = dci->pvt_info;
	struct ecc_error_info *pinf;

	if (p->ce_cnt) {
		pinf = &p->ceinfo;
		snprintf(priv->message, ZYNQMP_OCM_EDAC_MSG_SIZE,
			 "\n\rOCM ECC error type :%s\n\r"
			 "Addr: [0x%X]\n\rFault Data[31:0]: [0x%X]\n\r"
			 "Fault Data[63:32]: [0x%X]",
			 "CE", pinf->addr, pinf->data0, pinf->data1);
		edac_device_handle_ce(dci, 0, 0, priv->message);
	}

	if (p->ue_cnt) {
		pinf = &p->ueinfo;
		snprintf(priv->message, ZYNQMP_OCM_EDAC_MSG_SIZE,
			 "\n\rOCM ECC error type :%s\n\r"
			 "Addr: [0x%X]\n\rFault Data[31:0]: [0x%X]\n\r"
			 "Fault Data[63:32]: [0x%X]",
			 "UE", pinf->addr, pinf->data0, pinf->data1);
		edac_device_handle_ue(dci, 0, 0, priv->message);
	}

	memset(p, 0, sizeof(*p));
}
static void octeon_l2c_poll_oct1(struct edac_device_ctl_info *l2c)
{
	union cvmx_l2t_err l2t_err, l2t_err_reset;
	union cvmx_l2d_err l2d_err, l2d_err_reset;

	l2t_err_reset.u64 = 0;
	l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
	if (l2t_err.s.sec_err) {
		edac_device_handle_ce(l2c, 0, 0,
				      "Tag Single bit error (corrected)");
		l2t_err_reset.s.sec_err = 1;
	}
	if (l2t_err.s.ded_err) {
		edac_device_handle_ue(l2c, 0, 0,
				      "Tag Double bit error (detected)");
		l2t_err_reset.s.ded_err = 1;
	}
	if (l2t_err_reset.u64)
		cvmx_write_csr(CVMX_L2T_ERR, l2t_err_reset.u64);

	l2d_err_reset.u64 = 0;
	l2d_err.u64 = cvmx_read_csr(CVMX_L2D_ERR);
	if (l2d_err.s.sec_err) {
		edac_device_handle_ce(l2c, 0, 1,
				      "Data Single bit error (corrected)");
		l2d_err_reset.s.sec_err = 1;
	}
	if (l2d_err.s.ded_err) {
		edac_device_handle_ue(l2c, 0, 1,
				      "Data Double bit error (detected)");
		l2d_err_reset.s.ded_err = 1;
	}
	if (l2d_err_reset.u64)
		cvmx_write_csr(CVMX_L2D_ERR, l2d_err_reset.u64);

}
static irqreturn_t highbank_l2_err_handler(int irq, void *dev_id)
{
	struct edac_device_ctl_info *dci = dev_id;
	struct hb_l2_drvdata *drvdata = dci->pvt_info;

	if (irq == drvdata->sb_irq) {
		writel(1, drvdata->base + SR_CLR_SB_ECC_INTR);
		edac_device_handle_ce(dci, 0, 0, dci->ctl_name);
	}
	if (irq == drvdata->db_irq) {
		writel(1, drvdata->base + SR_CLR_DB_ECC_INTR);
		edac_device_handle_ue(dci, 0, 0, dci->ctl_name);
	}

	return IRQ_HANDLED;
}
Esempio n. 7
0
/**
 * pl310_edac_l2_parityerr_check - Check controller staus for parity errors
 * @dci:	Pointer to the edac device controller instance
 *
 * This routine is used to check and post parity errors
 */
static void pl310_edac_l2_parityerr_check(struct edac_device_ctl_info *dci)
{
	struct pl310_edac_l2_priv *priv = dci->pvt_info;
	u32 regval;

	regval = readl(priv->base + L2X0_RAW_INTR_STAT);
	if (regval & L2X0_INTR_PARRD_MASK) {
		/* Data parity error will be reported as correctable error */
		writel(L2X0_INTR_PARRD_MASK, priv->base + L2X0_INTR_CLEAR);
		edac_device_handle_ce(dci, 0, 0, dci->ctl_name);
	}
	if (regval & L2X0_INTR_PARRT_MASK) {
		/* tag parity error will be reported as uncorrectable error */
		writel(L2X0_INTR_PARRT_MASK, priv->base + L2X0_INTR_CLEAR);
		edac_device_handle_ue(dci, 0, 0, dci->ctl_name);
	}
}
static void _octeon_l2c_poll_oct2(struct edac_device_ctl_info *l2c, int tad)
{
	union cvmx_l2c_err_tdtx err_tdtx, err_tdtx_reset;
	union cvmx_l2c_err_ttgx err_ttgx, err_ttgx_reset;
	char buf1[64];
	char buf2[80];

	err_tdtx_reset.u64 = 0;
	err_tdtx.u64 = cvmx_read_csr(CVMX_L2C_ERR_TDTX(tad));
	if (err_tdtx.s.dbe || err_tdtx.s.sbe ||
	    err_tdtx.s.vdbe || err_tdtx.s.vsbe)
		snprintf(buf1, sizeof(buf1),
			 "type:%d, syn:0x%x, way:%d",
			 err_tdtx.s.type, err_tdtx.s.syn, err_tdtx.s.wayidx);

	if (err_tdtx.s.dbe) {
		snprintf(buf2, sizeof(buf2),
			 "L2D Double bit error (detected):%s", buf1);
		err_tdtx_reset.s.dbe = 1;
		edac_device_handle_ue(l2c, tad, 1, buf2);
	}
	if (err_tdtx.s.sbe) {
		snprintf(buf2, sizeof(buf2),
			 "L2D Single bit error (corrected):%s", buf1);
		err_tdtx_reset.s.sbe = 1;
		edac_device_handle_ce(l2c, tad, 1, buf2);
	}
	if (err_tdtx.s.vdbe) {
		snprintf(buf2, sizeof(buf2),
			 "VBF Double bit error (detected):%s", buf1);
		err_tdtx_reset.s.vdbe = 1;
		edac_device_handle_ue(l2c, tad, 1, buf2);
	}
	if (err_tdtx.s.vsbe) {
		snprintf(buf2, sizeof(buf2),
			 "VBF Single bit error (corrected):%s", buf1);
		err_tdtx_reset.s.vsbe = 1;
		edac_device_handle_ce(l2c, tad, 1, buf2);
	}
	if (err_tdtx_reset.u64)
		cvmx_write_csr(CVMX_L2C_ERR_TDTX(tad), err_tdtx_reset.u64);

	err_ttgx_reset.u64 = 0;
	err_ttgx.u64 = cvmx_read_csr(CVMX_L2C_ERR_TTGX(tad));

	if (err_ttgx.s.dbe || err_ttgx.s.sbe)
		snprintf(buf1, sizeof(buf1),
			 "type:%d, syn:0x%x, way:%d",
			 err_ttgx.s.type, err_ttgx.s.syn, err_ttgx.s.wayidx);

	if (err_ttgx.s.dbe) {
		snprintf(buf2, sizeof(buf2),
			 "Tag Double bit error (detected):%s", buf1);
		err_ttgx_reset.s.dbe = 1;
		edac_device_handle_ue(l2c, tad, 0, buf2);
	}
	if (err_ttgx.s.sbe) {
		snprintf(buf2, sizeof(buf2),
			 "Tag Single bit error (corrected):%s", buf1);
		err_ttgx_reset.s.sbe = 1;
		edac_device_handle_ce(l2c, tad, 0, buf2);
	}
	if (err_ttgx_reset.u64)
		cvmx_write_csr(CVMX_L2C_ERR_TTGX(tad), err_ttgx_reset.u64);
}