static void
nv30_vp_arith(struct nv30_vpc *vpc, int slot, int op,
struct nv30_sreg dst, int mask,
struct nv30_sreg s0, struct nv30_sreg s1,
struct nv30_sreg s2)
{
struct nv30_vertex_program *vp = vpc->vp;
uint32_t *hw;
vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
vpc->vpi = &vp->insns[vp->nr_insns - 1];
memset(vpc->vpi, 0, sizeof(*vpc->vpi));
vpc->vpi->const_index = -1;
hw = vpc->vpi->data;
hw[0] |= (NV30_VP_INST_COND_TR << NV30_VP_INST_COND_SHIFT);
hw[0] |= ((0 << NV30_VP_INST_COND_SWZ_X_SHIFT) |
(1 << NV30_VP_INST_COND_SWZ_Y_SHIFT) |
(2 << NV30_VP_INST_COND_SWZ_Z_SHIFT) |
(3 << NV30_VP_INST_COND_SWZ_W_SHIFT));
hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
// hw[3] |= NV30_VP_INST_SCA_DEST_TEMP_MASK;
// hw[3] |= (mask << NV30_VP_INST_VEC_WRITEMASK_SHIFT);
if (dst.type == NV30SR_OUTPUT) {
if (slot)
hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
else
hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
} else {
if (slot)
hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
else
hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
}
emit_dst(vpc, hw, slot, dst);
emit_src(vpc, hw, 0, s0);
emit_src(vpc, hw, 1, s1);
emit_src(vpc, hw, 2, s2);
}
void CCompiler::emit_insn(u8 opcode,struct nvfx_insn *insn)
{
u32 *hw;
u32 slot = opcode>>7;
u32 op = opcode&0x7f;
m_nCurInstruction = m_nInstructions++;
m_pInstructions = (struct vertex_program_exec*)realloc(m_pInstructions,m_nInstructions*sizeof(struct vertex_program_exec));
memset(&m_pInstructions[m_nCurInstruction],0,sizeof(struct vertex_program_exec));
hw = m_pInstructions[m_nCurInstruction].data;
emit_dst(hw,slot,insn);
emit_src(hw,0,&insn->src[0]);
emit_src(hw,1,&insn->src[1]);
emit_src(hw,2,&insn->src[2]);
hw[0] |= (insn->cc_cond << NVFX_VP(INST_COND_SHIFT));
hw[0] |= (insn->cc_test << NVFX_VP(INST_COND_TEST_SHIFT));
hw[0] |= (insn->cc_test_reg << NVFX_VP(INST_COND_REG_SELECT_SHIFT));
hw[0] |= ((insn->cc_swz[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
(insn->cc_swz[1] << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
(insn->cc_swz[2] << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
(insn->cc_swz[3] << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
if(insn->cc_update)
hw[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE);
if(insn->sat)
{
hw[0] |= NV40_VP_INST_SATURATE;
}
if (slot == 0) {
hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
hw[3] |= (insn->mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
} else {
hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK ;
hw[3] |= (insn->mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
}
}
void CCompilerFP::emit_insn(u8 op,struct nvfx_insn *insn)
{
u32 *hw;
bool have_const = false;
m_nCurInstruction = m_nInstructions;
grow_insns(1);
memset(&m_pInstructions[m_nCurInstruction],0,sizeof(struct fragment_program_exec));
hw = m_pInstructions[m_nCurInstruction].data;
if(op==NVFX_FP_OP_OPCODE_KIL)
m_nFPControl |= NV30_3D_FP_CONTROL_USES_KIL;
hw[0] |= (op << NVFX_FP_OP_OPCODE_SHIFT);
hw[0] |= (insn->mask << NVFX_FP_OP_OUTMASK_SHIFT);
hw[0] |= (insn->precision << NVFX_FP_OP_PRECISION_SHIFT);
hw[2] |= (insn->scale << NVFX_FP_OP_DST_SCALE_SHIFT);
if(insn->sat)
hw[0] |= NVFX_FP_OP_OUT_SAT;
if(insn->cc_update)
hw[0] |= NVFX_FP_OP_COND_WRITE_ENABLE;
hw[1] |= (insn->cc_cond << NVFX_FP_OP_COND_SHIFT);
hw[1] |= ((insn->cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
(insn->cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
(insn->cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
(insn->cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
if(insn->unit >= 0) {
hw[0] |= (insn->unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
m_nSamplers |= (1<<insn->unit);
}
emit_dst(&insn->dst,&have_const);
emit_src(0,&insn->src[0],&have_const);
emit_src(1,&insn->src[1],&have_const);
emit_src(2,&insn->src[2],&have_const);
}
