// Important! adr has to be 5-bytes length even if MSB bytes are unused uint8_t configRxPipe(uint8_t pipe_nr, uint8_t *adr, uint8_t plLen, uint8_t en_aa) { uint8_t tmp; uint8_t nr = pipe_nr; if(plLen > 32 || nr > 5 || en_aa > 1){ return 0; } // write address if(nr<2) // full length for rx pipe 0 an 1 writeRegCmdBuf(RFM7x_CMD_WRITE_REG | (RFM7x_REG_RX_ADDR_P0 + nr), adr, 5); else // only LSB for pipes 2..5 writeRegVal(RFM7x_CMD_WRITE_REG | (RFM7x_REG_RX_ADDR_P0 + nr), adr[0]); // static if (plLen) { // set payload len writeRegVal(RFM7x_CMD_WRITE_REG | (RFM7x_REG_RX_PW_P0 + nr), plLen); // set EN_AA bit tmp = readRegVal(RFM7x_REG_EN_AA); if (en_aa) tmp |= 1 << nr; else tmp &= ~(1 << nr); writeRegVal(RFM7x_CMD_WRITE_REG | RFM7x_REG_EN_AA, tmp); // clear DPL bit tmp = readRegVal(RFM7x_REG_DYNPD); tmp &= ~(1 << nr); writeRegVal(RFM7x_CMD_WRITE_REG | RFM7x_REG_DYNPD, tmp); // set Enable pipe bit enableRxPipe(nr); } // dynamic else { // set payload len to default writeRegVal(RFM7x_CMD_WRITE_REG | (RFM7x_REG_RX_PW_P0 + nr), 0x20); // set EN_AA bit tmp = readRegVal(RFM7x_REG_EN_AA); tmp |= 1 << nr; writeRegVal(RFM7x_CMD_WRITE_REG | RFM7x_REG_EN_AA, tmp); // set DPL bit tmp = readRegVal(RFM7x_REG_DYNPD); tmp |= 1 << nr; writeRegVal(RFM7x_CMD_WRITE_REG | RFM7x_REG_DYNPD, tmp); // set Enable pipe bit enableRxPipe(nr); } return 1; }
uint8_t RFM70::configRxPipe(uint8_t pipe_nr, uint8_t * adr, uint8_t plLen, uint8_t en_aa) { uint8_t tmp; uint8_t nr = pipe_nr - 1; if (plLen > 32 || nr > 5 || en_aa > 1) { return 0; } // write address // full length for rx pipe 0 an 1 if (nr < 2) { writeRegCmdBuf(RFM70_CMD_WRITE_REG | (RFM70_REG_RX_ADDR_P0 + nr), adr, sizeof(adr)); } else { // only LSB for pipes 2..5 writeRegVal(RFM70_CMD_WRITE_REG | (RFM70_REG_RX_ADDR_P0 + nr), adr[0]); //ODO:check this } // static if (plLen) { // set payload len writeRegVal(RFM70_CMD_WRITE_REG | (RFM70_REG_RX_PW_P0 + nr), plLen); // set EN_AA bit tmp = readRegVal(RFM70_REG_EN_AA); if (en_aa) { tmp |= 1 << nr; } else { tmp &= ~(1 << nr); } writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_EN_AA, tmp); // clear DPL bit tmp = readRegVal(RFM70_REG_DYNPD); tmp &= ~(1 << nr); writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_DYNPD, tmp); // set Enable pipe bit enableRxPipe(nr); } else { // set payload len to default writeRegVal(RFM70_CMD_WRITE_REG | (RFM70_REG_RX_PW_P0 + nr), 0x20); // set EN_AA bit tmp = readRegVal(RFM70_REG_EN_AA); tmp |= 1 << nr; writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_EN_AA, tmp); // set DPL bit tmp = readRegVal(RFM70_REG_DYNPD); tmp |= 1 << nr; writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_DYNPD, tmp); // set Enable pipe bit enableRxPipe(nr); } return 1; }