void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, const struct dmm_lisa_map_regs *lisa_regs, int nrs) { int i; enable_emif_clocks(); for (i = 0; i < nrs; i++) ddr_init_settings(ctrl, i); enable_dmm_clocks(); /* Program the DMM to for non-interleaved configuration */ config_dmm(lisa_regs); /* Program EMIF CFG Registers */ for (i = 0; i < nrs; i++) { set_sdram_timings(regs, i); config_sdram(regs, i); } udelay(1000); for (i = 0; i < nrs; i++) ddr3_sw_levelling(data, i); udelay(50000); /* Some delay needed */ }
void config_dmm(const struct dmm_lisa_map_regs *regs) { enable_dmm_clocks(); writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); }