static int bfin_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct bfin_pwm *priv = pwm_get_chip_data(pwm);
enable_gptimer(priv->pin);
return 0;
}
//Config PA1 as an PWM output pin
void initPWM()
{
//Timer is 16Mhz
/* Enable module clock for the GPTx in Active mode, GPT0 clock enable, CPU running */
REG(SYS_CTRL_RCGCGPT) |= SYS_CTRL_RCGCGPT_GPT0;
disable_gptimer();
/* Use 16-bit timer */
REG(GPT_CONF_BASE + GPTIMER_CFG) = 0x04;
/* Configure PWM mode, 0x00000008 Timer A alternate mode. */
REG(GPT_CONF_BASE + GPTIMER_TAMR) = 0;
REG(GPT_CONF_BASE + GPTIMER_TAMR) |= GPTIMER_TAMR_TAAMS;
/* To enable PWM mode, the TACM bit must be cleared and the lowest 2 bits
(TAMR) field must be configured to 0x2.
GPTIMER_TnMR bit values, GPTIMER_TAMR_TAMR_PERIODIC is 0x00000002 */
REG(GPT_CONF_BASE + GPTIMER_TAMR) |= GPTIMER_TAMR_TAMR_PERIODIC;
//how often the counter is incremented: every pre-scaler / clock 16000000 seconds
REG(GPT_CONF_BASE + GPTIMER_TAPR) = 0; //PRESCALER_VALUE
/* Set the start value (period), count down */
REG(GPT_CONF_BASE+ GPTIMER_TAILR) = 16000; //frequency: 1kHz. 16000: 3E80, 16000000:F42400
/* Set the deassert period */
REG(GPT_CONF_BASE + GPTIMER_TAMATCHR) = 12800; //duty cycle: 20% so vibrator time is 20%. 800: 0x1F40, 8000000: 7A1200
// Defined in contiki/cpu/cc2538/dev/ioc.h
/* Function select for Port:Pin.
The third param sel can be any of the IOC_PXX_SEL_xyz defines.
For example, IOC_PXX_SEL_UART0_TXD will set the port to act as UART0 TX.
Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the GPT0OCP1.
Configure pin : PA:1 selected as GPT0OCP1*/
ioc_set_sel(PWM_GPIO_CONF_PORT, PWM_GPIO_CONF_PIN, IOC_CONF_SEL);
/* Set Port:Pin override function, IOC_OVERRIDE_OE: Output */
ioc_set_over(PWM_GPIO_CONF_PORT, PWM_GPIO_CONF_PIN, IOC_OVERRIDE_OE);
/* Configure the pin to be under peripheral control with PIN_MASK of port with PORT_BASE.*/
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(PWM_GPIO_CONF_PORT), GPIO_PIN_MASK(PWM_GPIO_CONF_PIN));
enable_gptimer();
}
int pwm_enable(struct pwm_device *pwm)
{
enable_gptimer(pwm->id);
return 0;
}
rtems_task Init( rtems_task_argument ignored ) {
//printk( "*** HELLO WORLD TEST PRINTK ***\n" );
//debug( "*** HELLO WORLD TEST DEBUG ***\n" );
printf( "reg (addr = %p) = %X\n", (void*)0x00000018, readl( 0x00000018 ) );
int j = 0;
for( j = 17; j < 96; j++ ) {
timer_interrupt_handler_install( j );
}
bla();
print_gptimer();
print_intc();
writel( 0xFFFFFFDF, &intc_base->bla[ 1 ].INTCPS_MIR );
enable_gptimer();
rtems_interrupt_level level;
rtems_interrupt_disable( level );
print_gptimer();
print_intc();
/* disable_wdts();
WDTIMER2_WCLR = ENABLE_WDT_PRESCALER | SET_WDT_PRESCALER( 1 );
WDTIMER3_WCLR = ENABLE_WDT_PRESCALER | SET_WDT_PRESCALER( 1 );
WDTIMER2_WLDR = 0xFFFFFFF0;
WDTIMER3_WLDR = 0xFFFFFFF0;
WDTIMER2_WTGR = 0x00000001;
WDTIMER3_WTGR = 0x00000001;
check_reg( 0x48314024 );
check_reg( 0x49030024 );
check_reg( 0x48314030 );
check_reg( 0x49030030 );
check_reg( 0x4831402C );
check_reg( 0x4903002C );
check_reg( 0x48314018 );
check_reg( 0x49030018 );
enable_wdts();
printf( "WDTIMER2_WCRR = %X\n", WDTIMER2_WCRR );
printf( "WDTIMER3_WCRR = %X\n", WDTIMER2_WCRR );*/
/*i2c_init( CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE );
imw( 0x4B, 0x29, 0x00 );
imw( 0x4B, 0x1C, 0x36 );
imw( 0x4B, 0x1D, 0x54 );
imw( 0x4B, 0x1E, 0x20 );
imw( 0x4B, 0x1F, 0x07 );
imw( 0x4B, 0x20, 0x08 );
imw( 0x4B, 0x21, 0x12 );
imw( 0x4B, 0x29, 0x01 );
imd( 0x4B, 0x2A, 1 );*/
int i;
for( i = 0; i < 10; i++ ) {
//udelay( 500000 );
//imd( 0x4B, 0x1C, 10 );
//printf( "WDTIMER2_WCRR = %X\n", WDTIMER2_WCRR );
//printf( "WDTIMER3_WCRR = %X\n", WDTIMER2_WCRR );
//check_reg( 0x48314018 );
//check_reg( 0x49030018 );
print_gptimer();
print_intc();
}
rtems_interrupt_enable( level );
print_gptimer();
print_intc();
/*
imw 0x4A 0x0D 0x00
imw 0x4A 0x00 0x36
imw 0x4A 0x01 0x54
imw 0x4A 0x02 0x90
imw 0x4A 0x03 0x05
imw 0x4A 0x04 0x09
imw 0x4A 0x05 0x97
imw 0x4A 0x0D 0x01
imd 0x4A 0x00 10
*/
//printf( "*** HELLO WORLD TEST PRINTF ***\n" );
exit( 0 );
}
