int amazon_se_eth_init(bd_t * bis)
{
struct eth_device *dev;
if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
{
printf("Failed to allocate memory\n");
return 0;
}
memset(dev, 0, sizeof(*dev));
amazon_se_dma_init();
#ifdef CONFIG_ETHERNET_TYPE_EPHY
amazon_se_sw_chip_init(EPHY_MODE, 0);
#endif
#ifdef CONFIG_ETHERNET_TYPE_RMII
amazon_se_sw_chip_init(RED_MII_MODE, 1);
#endif
sprintf(dev->name, "AMAZON_SE Switch");
dev->init = amazon_se_switch_init;
dev->halt = amazon_se_switch_halt;
dev->send = amazon_se_switch_send;
dev->recv = amazon_se_switch_recv;
eth_register(dev);
return 1;
}
int fec_initialize(bd_t *bis)
{
struct eth_device* dev;
int i;
for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
{
dev = (struct eth_device*) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "FCC%d",
ether_fcc_info[i].ether_index + 1);
dev->priv = ðer_fcc_info[i];
dev->init = fec_init;
dev->halt = fec_halt;
dev->send = fec_send;
dev->recv = fec_recv;
eth_register(dev);
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
&& defined(CONFIG_BITBANGMII)
miiphy_register(dev->name,
bb_miiphy_read, bb_miiphy_write);
#endif
}
return 1;
}
int owl_mac_initialize(bd_t *bis)
{
struct owl_mac_info *priv;
struct eth_device *dev;
priv = (struct owl_mac_info *)malloc(sizeof(*priv));
if(!priv)
return -1;
if(owl_mac_parse_fdtdec(priv))
return -1;
dev = (struct eth_device *)malloc(sizeof(*dev));
if(!dev){
free(priv);
return -1;
}
dev->init = owl_mac_init;
dev->halt = owl_mac_halt;
dev->send = owl_mac_send;
dev->recv = owl_mac_recv;
dev->write_hwaddr = owl_mac_set_macaddr;
dev->priv = priv;
sprintf(dev->name, "owl_mac");
eth_register(dev);
//owl_mac_power_on(dev);
return 0;
}
static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
phy_interface_t enet_if)
{
int err;
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
sprintf(net_dev->name, "DPMAC%d@%s", priv->dpmac_id,
phy_interface_strings[enet_if]);
net_dev->iobase = 0;
net_dev->init = ldpaa_eth_open;
net_dev->halt = ldpaa_eth_stop;
net_dev->send = ldpaa_eth_tx;
net_dev->recv = ldpaa_eth_pull_dequeue_rx;
/*
TODO: PHY MDIO information
priv->bus = info->bus;
priv->phyaddr = info->phy_addr;
priv->enet_if = info->enet_if;
*/
if (init_phy(net_dev))
return 0;
err = eth_register(net_dev);
if (err < 0) {
printf("eth_register() = %d\n", err);
return err;
}
return 0;
}
int ar7100_initialize(bd_t *bis)
{
struct eth_device *dev;
debug ("Register ar7100 driver.\n");
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if(dev == NULL)
{
printf("Allocate memory for eth device fail.\n");
return NULL;
}
dev->init = ag7100_start;
dev->halt = ag7100_stop;
dev->send = ag7100_send;
dev->recv = ag7100_poll;
dev->priv = &ag7100_priv_data0;
ag7100_init(dev, bis);
eth_register(dev);
return 0;
}
static int netx_eth_probe(struct device_d *dev)
{
struct eth_device *edev;
struct netx_eth_priv *priv;
struct netx_eth_platform_data *pdata;
debug("netx_eth_probe()\n");
pdata = dev->platform_data;
edev = xzalloc(sizeof(struct eth_device) + sizeof(struct netx_eth_priv));
edev->priv = (struct netx_priv *)(edev + 1);
priv = edev->priv;
priv->xcno = pdata->xcno;
edev->init = netx_eth_init_dev;
edev->open = netx_eth_open;
edev->send = netx_eth_send;
edev->recv = netx_eth_rx;
edev->halt = netx_eth_halt;
edev->get_ethaddr = netx_eth_get_ethaddr;
edev->set_ethaddr = netx_eth_set_ethaddr;
edev->parent = dev;
priv->miibus.read = netx_miibus_read;
priv->miibus.write = netx_miibus_write;
priv->miibus.parent = dev;
netx_eth_init_phy();
mdiobus_register(&priv->miibus);
eth_register(edev);
return 0;
}
int cs8900_initialize(u8 dev_num, int base_addr)
{
struct eth_device *dev;
struct cs8900_priv *priv;
dev = malloc(sizeof(*dev));
if (!dev) {
return 0;
}
memset(dev, 0, sizeof(*dev));
priv = malloc(sizeof(*priv));
if (!priv) {
free(dev);
return 0;
}
memset(priv, 0, sizeof(*priv));
priv->regs = (struct cs8900_regs *)base_addr;
dev->iobase = base_addr;
dev->priv = priv;
dev->init = cs8900_init;
dev->halt = cs8900_halt;
dev->send = cs8900_send;
dev->recv = cs8900_recv;
/* Load MAC address from EEPROM */
cs8900_get_enetaddr(dev);
sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
eth_register(dev);
return 0;
}
static int cs8900_probe(struct device_d *dev)
{
struct eth_device *edev;
struct cs8900_priv *priv;
debug("cs8900_init()\n");
priv = (struct cs8900_priv *)xmalloc(sizeof(*priv));
priv->regs = dev_request_mem_region(dev, 0);
if (cs8900_check_id(priv)) {
free(priv);
return -1;
}
edev = (struct eth_device *)xmalloc(sizeof(struct eth_device));
edev->priv = priv;
edev->init = cs8900_dev_init;
edev->open = cs8900_open;
edev->send = cs8900_send;
edev->recv = cs8900_recv;
edev->halt = cs8900_halt;
edev->get_ethaddr = cs8900_get_ethaddr;
edev->set_ethaddr = cs8900_set_ethaddr;
edev->parent = dev;
eth_register(edev);
return 0;
}
static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
phy_interface_t enet_if)
{
int err;
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
sprintf(net_dev->name, "DPMAC%d@%s", priv->dpmac_id,
phy_interface_strings[enet_if]);
net_dev->iobase = 0;
net_dev->init = ldpaa_eth_open;
net_dev->halt = ldpaa_eth_stop;
net_dev->send = ldpaa_eth_tx;
net_dev->recv = ldpaa_eth_pull_dequeue_rx;
#ifdef CONFIG_PHYLIB
err = init_phy(net_dev);
if (err < 0)
return err;
#endif
err = eth_register(net_dev);
if (err < 0) {
printf("eth_register() = %d\n", err);
return err;
}
return 0;
}
int au1x00_enet_initialize(bd_t *bis){
struct eth_device* dev;
if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
puts ("malloc failed\n");
return -1;
}
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "Au1X00 ethernet");
dev->iobase = 0;
dev->priv = 0;
dev->init = au1x00_init;
dev->halt = au1x00_halt;
dev->send = au1x00_send;
dev->recv = au1x00_recv;
eth_register(dev);
#if defined(CONFIG_CMD_MII)
miiphy_register(dev->name,
au1x00_miiphy_read, au1x00_miiphy_write);
#endif
return 1;
}
/*
* This function initializes the EMAC hardware.
*/
int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
{
int res;
struct eth_device *dev;
struct phy_device *phy_dev;
dev = malloc(sizeof(struct eth_device));
if (dev == NULL)
return -1;
memset(dev, 0, sizeof(struct eth_device));
strcpy(dev->name, eth_priv->int_name);
dev->priv = eth_priv;
keystone2_eth_read_mac_addr(dev);
dev->iobase = 0;
dev->init = keystone2_eth_open;
dev->halt = keystone2_eth_close;
dev->send = keystone2_eth_send_packet;
dev->recv = keystone2_eth_rcv_packet;
#ifdef CONFIG_MCAST_TFTP
dev->mcast = keystone2_eth_bcast_addr;
#endif
eth_register(dev);
/* Register MDIO bus if it's not registered yet */
if (!mdio_bus) {
mdio_bus = mdio_alloc();
mdio_bus->read = keystone2_mdio_read;
mdio_bus->write = keystone2_mdio_write;
mdio_bus->reset = keystone2_mdio_reset;
mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
sprintf(mdio_bus->name, "ethernet-mdio");
res = mdio_register(mdio_bus);
if (res)
return res;
}
#ifndef CONFIG_SOC_K2G
keystone2_net_serdes_setup();
#endif
/* Create phy device and bind it with driver */
#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
dev, eth_priv->phy_if);
phy_config(phy_dev);
#else
phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
eth_priv->phy_if);
phy_dev->dev = dev;
#endif
eth_priv->phy_dev = phy_dev;
return 0;
}
int bfin_EMAC_initialize(bd_t *bis)
{
struct eth_device *dev;
dev = malloc(sizeof(*dev));
if (dev == NULL)
hang();
memset(dev, 0, sizeof(*dev));
strcpy(dev->name, "bfin_mac");
dev->iobase = 0;
dev->priv = 0;
dev->init = bfin_EMAC_init;
dev->halt = bfin_EMAC_halt;
dev->send = bfin_EMAC_send;
dev->recv = bfin_EMAC_recv;
dev->write_hwaddr = bfin_EMAC_setup_addr;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
#endif
return 0;
}
int tap_probe(struct device_d *dev)
{
struct eth_device *edev;
struct tap_priv *priv;
int ret = 0;
priv = xzalloc(sizeof(struct tap_priv));
priv->name = "barebox";
priv->fd = tap_alloc(priv->name);
if (priv->fd < 0) {
ret = priv->fd;
goto out;
}
edev = xzalloc(sizeof(struct eth_device));
edev->priv = priv;
edev->parent = dev;
edev->init = tap_eth_open;
edev->open = tap_eth_open;
edev->send = tap_eth_send;
edev->recv = tap_eth_rx;
edev->halt = tap_eth_halt;
edev->get_ethaddr = tap_get_ethaddr;
edev->set_ethaddr = tap_set_ethaddr;
eth_register(edev);
return 0;
out:
free(priv);
return ret;
}
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
struct eth_device *netdev;
u32 ncfgr;
macb = malloc(sizeof(struct macb_device));
if (!macb) {
printf("Error: Failed to allocate memory for MACB%d\n", id);
return -1;
}
memset(macb, 0, sizeof(struct macb_device));
netdev = &macb->netdev;
macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE,
&macb->rx_buffer_dma);
macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE
* sizeof(struct macb_dma_desc),
&macb->rx_ring_dma);
macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE
* sizeof(struct macb_dma_desc),
&macb->tx_ring_dma);
macb->regs = regs;
macb->phy_addr = phy_addr;
if (macb_is_gem(macb))
sprintf(netdev->name, "gmac%d", id);
else
sprintf(netdev->name, "macb%d", id);
netdev->init = macb_init;
netdev->halt = macb_halt;
netdev->send = macb_send;
netdev->recv = macb_recv;
netdev->write_hwaddr = macb_write_hwaddr;
/*
* Do some basic initialization so that we at least can talk
* to the PHY
*/
if (macb_is_gem(macb)) {
ncfgr = gem_mdc_clk_div(id, macb);
ncfgr |= GEM_BF(DBW, 1);
} else {
ncfgr = macb_mdc_clk_div(id, macb);
}
macb_writel(macb, NCFGR, ncfgr);
eth_register(netdev);
#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write);
macb->bus = miiphy_get_dev_by_name(netdev->name);
#endif
return 0;
}
/*
* Initialize device structure. Returns success if
* initialization succeeded.
*/
static int gfar_probe(struct device_d *dev)
{
struct gfar_info_struct *gfar_info = dev->platform_data;
struct eth_device *edev;
struct gfar_private *priv;
size_t size;
char *p;
priv = xzalloc(sizeof(struct gfar_private));
if (NULL == priv)
return -ENODEV;
edev = &priv->edev;
priv->regs = dev_request_mem_region(dev, 0);
priv->phyregs = dev_request_mem_region(dev, 1);
priv->phyregs_sgmii = dev_request_mem_region(dev, 2);
priv->phyaddr = gfar_info->phyaddr;
priv->tbicr = gfar_info->tbicr;
priv->tbiana = gfar_info->tbiana;
/*
* Allocate descriptors 64-bit aligned. Descriptors
* are 8 bytes in size.
*/
size = ((TX_BUF_CNT * sizeof(struct txbd8)) +
(RX_BUF_CNT * sizeof(struct rxbd8))) + BUF_ALIGN;
p = (char *)xmemalign(BUF_ALIGN, size);
priv->txbd = (struct txbd8 *)p;
priv->rxbd = (struct rxbd8 *)(p + (TX_BUF_CNT * sizeof(struct txbd8)));
edev->priv = priv;
edev->init = gfar_init;
edev->open = gfar_open;
edev->halt = gfar_halt;
edev->send = gfar_send;
edev->recv = gfar_recv;
edev->get_ethaddr = gfar_get_ethaddr;
edev->set_ethaddr = gfar_set_ethaddr;
edev->parent = dev;
setbits_be32(priv->regs + GFAR_MACCFG1_OFFSET, GFAR_MACCFG1_SOFT_RESET);
udelay(2);
clrbits_be32(priv->regs + GFAR_MACCFG1_OFFSET, GFAR_MACCFG1_SOFT_RESET);
priv->miibus.read = gfar_miiphy_read;
priv->miibus.write = gfar_miiphy_write;
priv->miibus.priv = priv;
priv->miibus.parent = dev;
gfar_init_phy(edev);
mdiobus_register(&priv->miibus);
return eth_register(edev);
}
int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
int phy_addr, u32 emio)
{
struct eth_device *dev;
struct zynq_gem_priv *priv;
void *bd_space;
dev = calloc(1, sizeof(*dev));
if (dev == NULL)
return -1;
dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
if (dev->priv == NULL) {
free(dev);
return -1;
}
priv = dev->priv;
/* Align rxbuffers to ARCH_DMA_MINALIGN */
priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
/* Align bd_space to MMU_SECTION_SHIFT */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
BD_SPACE, DCACHE_OFF);
/* Initialize the bd spaces for tx and rx bd's */
priv->tx_bd = (struct emac_bd *)bd_space;
priv->rx_bd = (struct emac_bd *)((unsigned long)bd_space +
BD_SEPRN_SPACE);
priv->phyaddr = phy_addr;
priv->emio = emio;
#ifndef CONFIG_ZYNQ_GEM_INTERFACE
priv->interface = PHY_INTERFACE_MODE_MII;
#else
priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
#endif
sprintf(dev->name, "Gem.%lx", base_addr);
dev->iobase = base_addr;
dev->init = zynq_gem_init;
dev->halt = zynq_gem_halt;
dev->send = zynq_gem_send;
dev->recv = zynq_gem_recv;
dev->write_hwaddr = zynq_gem_setup_mac;
eth_register(dev);
miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
priv->bus = miiphy_get_dev_by_name(dev->name);
return 1;
}
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
struct eth_device *netdev;
unsigned long macb_hz;
u32 ncfgr;
macb = malloc(sizeof(struct macb_device));
if (!macb) {
printf("Error: Failed to allocate memory for MACB%d\n", id);
return -1;
}
memset(macb, 0, sizeof(struct macb_device));
netdev = &macb->netdev;
macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE,
&macb->rx_buffer_dma);
macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE
* sizeof(struct macb_dma_desc),
&macb->rx_ring_dma);
macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE
* sizeof(struct macb_dma_desc),
&macb->tx_ring_dma);
macb->regs = regs;
macb->phy_addr = phy_addr;
sprintf(netdev->name, "macb%d", id);
netdev->init = macb_init;
netdev->halt = macb_halt;
netdev->send = macb_send;
netdev->recv = macb_recv;
netdev->write_hwaddr = macb_write_hwaddr;
/*
* Do some basic initialization so that we at least can talk
* to the PHY
*/
macb_hz = get_macb_pclk_rate(id);
if (macb_hz < 20000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
else if (macb_hz < 40000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
else if (macb_hz < 80000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
else
ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
macb_writel(macb, NCFGR, ncfgr);
eth_register(netdev);
#if defined(CONFIG_CMD_MII)
miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write);
#endif
return 0;
}
int pch_gbe_register(bd_t *bis)
{
struct eth_device *dev;
struct pch_gbe_priv *priv;
pci_dev_t devno;
u32 iobase;
devno = pci_find_devices(supported, 0);
if (devno == -1)
return -ENODEV;
dev = (struct eth_device *)malloc(sizeof(*dev));
if (!dev)
return -ENOMEM;
memset(dev, 0, sizeof(*dev));
/*
* The priv structure contains the descriptors and frame buffers which
* need a strict buswidth alignment (64 bytes)
*/
priv = (struct pch_gbe_priv *)memalign(PCH_GBE_ALIGN_SIZE,
sizeof(*priv));
if (!priv) {
free(dev);
return -ENOMEM;
}
memset(priv, 0, sizeof(*priv));
dev->priv = priv;
priv->dev = dev;
priv->bdf = devno;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
iobase = pci_mem_to_phys(devno, iobase);
dev->iobase = iobase;
priv->mac_regs = (struct pch_gbe_regs *)iobase;
sprintf(dev->name, "pch_gbe.%x", iobase);
/* Read MAC address from SROM and initialize dev->enetaddr with it */
pch_gbe_mac_read(priv->mac_regs, dev->enetaddr);
dev->init = pch_gbe_init;
dev->halt = pch_gbe_halt;
dev->send = pch_gbe_send;
dev->recv = pch_gbe_recv;
eth_register(dev);
priv->interface = PHY_INTERFACE_MODE_RGMII;
pch_gbe_mdio_init(dev->name, priv->mac_regs);
priv->bus = miiphy_get_dev_by_name(dev->name);
return pch_gbe_phy_init(dev);
}
int rtl8169_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
unsigned int region;
u16 device;
/* Find RTL8169 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_word(devno, PCI_DEVICE_ID, &device);
switch (device) {
case 0x8168:
region = 2;
break;
default:
region = 1;
break;
}
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
iobase &= ~0xf;
debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
if (!dev) {
printf("Can not allocate memory of rtl8169\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8169#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)pci_mem_to_phys(devno, iobase);
dev->init = rtl_reset;
dev->halt = rtl_halt;
dev->send = rtl_send;
dev->recv = rtl_recv;
eth_register (dev);
rtl_init(dev, bis);
card_number++;
}
return card_number;
}
int sh_eth_initialize(bd_t *bd)
{
int ret = 0;
struct sh_eth_dev *eth = NULL;
struct eth_device *dev = NULL;
eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
if (!eth) {
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
ret = -ENOMEM;
goto err;
}
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev) {
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
ret = -ENOMEM;
goto err;
}
memset(dev, 0, sizeof(struct eth_device));
memset(eth, 0, sizeof(struct sh_eth_dev));
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
dev->priv = (void *)eth;
dev->iobase = 0;
dev->init = sh_eth_init;
dev->halt = sh_eth_halt;
dev->send = sh_eth_send;
dev->recv = sh_eth_recv;
eth->port_info[eth->port].dev = dev;
sprintf(dev->name, SHETHER_NAME);
/* Register Device to EtherNet subsystem */
eth_register(dev);
bb_miiphy_buses[0].priv = eth;
miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
puts("Please set MAC address\n");
return ret;
err:
if (dev)
free(dev);
if (eth)
free(eth);
printf(SHETHER_NAME ": Failed\n");
return ret;
}
int uec_initialize(bd_t *bis, uec_info_t *uec_info)
{
struct eth_device *dev;
int i;
uec_private_t *uec;
int err;
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev)
return 0;
memset(dev, 0, sizeof(struct eth_device));
/* Allocate the UEC private struct */
uec = (uec_private_t *)malloc(sizeof(uec_private_t));
if (!uec) {
return -ENOMEM;
}
memset(uec, 0, sizeof(uec_private_t));
/* Adjust uec_info */
#if (MAX_QE_RISC == 4)
uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
#endif
devlist[uec_info->uf_info.ucc_num] = dev;
uec->uec_info = uec_info;
uec->dev = dev;
sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
dev->iobase = 0;
dev->priv = (void *)uec;
dev->init = uec_init;
dev->halt = uec_halt;
dev->send = uec_send;
dev->recv = uec_recv;
/* Clear the ethnet address */
for (i = 0; i < 6; i++)
dev->enetaddr[i] = 0;
eth_register(dev);
err = uec_startup(uec);
if (err) {
printf("%s: Cannot configure net device, aborting.",dev->name);
return err;
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
#endif
return 1;
}
int MDrv_EMAC_initialize(const bd_t * bis)
{
struct eth_device *nic = NULL;
struct emac_hw *hw = NULL;
char* phy_id_string=NULL;
phy_id_string = getenv ("PHY_ID");
if (phy_id_string != NULL)
{
//phy_id =phy_id_string ? (int)simple_strtol(phy_id_string, NULL, 10) : 0;
phy_id =(int)simple_strtol(phy_id_string, NULL, 10);
}
if(emac_init)
{
MDrv_EMAC_PhyAddrScan();
#if (EMAC_DBG_TFTP)
rxpre_seq = txpre_seq = 0;
#endif
return -1;
}
if (!MDrv_EMAC_VarInit())
return -1;
nic=&nic_device;
hw=&hw_device;
hw->dlist_phys = hw->dlist = (struct recv_desc_bufs *) (RX_BUFFER_BASE|RAM_ADDR_BASE);
printf("%s->%d\n",__FILE__,__LINE__);
//asm __volatile__ ("abc: ; b abc;");
MHal_EMAC_Power_On_Clk();
printf("%s->%d\n",__FILE__,__LINE__);
//asm __volatile__ ("abc: ; b abc;");
MDrv_EMAC_PhyAddrScan();
printf("%s->%d\n",__FILE__,__LINE__);
MDrv_EMAC_PatchPHY();
nic->priv = hw;
MDrv_EMAC_HW_init(nic);
/* EMAC HW init */
nic->init = MDrv_EMAC_open;
nic->recv = MDrv_EMAC_rx;
nic->send = MDrv_EMAC_tx;
nic->halt = MDrv_EMAC_close;
memcpy(nic->enetaddr, ThisBCE.sa1, sizeof(ThisBCE.sa1));
eth_register(nic);
emac_init=1;
return 0;
//test start
}
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
*/
static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
{
struct eth_device *dev;
int i;
struct tsec_private *priv;
dev = (struct eth_device *)malloc(sizeof *dev);
if (NULL == dev)
return 0;
memset(dev, 0, sizeof *dev);
priv = (struct tsec_private *)malloc(sizeof(*priv));
if (NULL == priv)
return 0;
privlist[num_tsecs++] = priv;
priv->regs = tsec_info->regs;
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr;
priv->flags = tsec_info->flags;
sprintf(dev->name, tsec_info->devname);
priv->interface = tsec_info->interface;
priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
dev->iobase = 0;
dev->priv = priv;
dev->init = tsec_init;
dev->halt = tsec_halt;
dev->send = tsec_send;
dev->recv = tsec_recv;
#ifdef CONFIG_MCAST_TFTP
dev->mcast = tsec_mcast_addr;
#endif
/* Tell u-boot to get the addr from the env */
for (i = 0; i < 6; i++)
dev->enetaddr[i] = 0;
eth_register(dev);
/* Reset the MAC */
setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
/* Try to initialize PHY here, and return */
return init_phy(dev);
}
int plb2800_eth_initialize(bd_t * bis)
{
struct eth_device *dev;
ulong temp;
#ifdef DEBUG
printf("Entered plb2800_eth_initialize()\n");
#endif
if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
{
printf("Failed to allocate memory\n");
return -1;
}
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "PLB2800 Switch");
dev->init = plb2800_eth_init;
dev->halt = plb2800_eth_halt;
dev->send = plb2800_eth_send;
dev->recv = plb2800_eth_recv;
eth_register(dev);
/* bug fix */
*(ulong *)0xb800e800 = 0x838;
/* Set MBOX ownership */
temp = CMAC_CRIT << MBOX_STAT_ID_SHF;
MBOX_REG(0)->stat = temp;
MBOX_REG(1)->stat = temp;
temp = CMAC_NON_CRIT << MBOX_STAT_ID_SHF;
MBOX_REG(2)->stat = temp;
MBOX_REG(3)->stat = temp;
plb2800_set_mac_addr(dev, plb2800_get_mac_addr());
/* Disable all Mbox interrupt */
temp = MIPS_H_MASK;
temp &= ~ (SW_H_MBOX1_MASK | SW_H_MBOX2_MASK | SW_H_MBOX3_MASK | SW_H_MBOX4_MASK) ;
MIPS_H_MASK = temp;
#ifdef DEBUG
printf("Leaving plb2800_eth_initialize()\n");
#endif
return 0;
}
int jz_enet_initialize(bd_t *bis)
{
u32 reg;
dev = (struct eth_device *) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
#if defined(CONFIG_JZ4740)
#define RD_N_PIN (32 + 29)
#define WE_N_PIN (32 + 30)
#define CS4_PIN (32 + 28)
__gpio_as_func0(CS4_PIN);
__gpio_as_func0(RD_N_PIN);
__gpio_as_func0(WE_N_PIN);
reg = REG_EMC_SMCR4;
reg = (reg & (~EMC_SMCR_BW_MASK)) | EMC_SMCR_BW_16BIT;
REG_EMC_SMCR4 = reg;
dev->iobase = 0xa8000000;
#elif defined(CONFIG_JZ4750)
#if !defined(CONFIG_AQUILA)
#define RD_N_PIN (32*2 +25)
#define WE_N_PIN (32*2 +26)
#define CS3_PIN (32*2 +23)
__gpio_as_func0(CS3_PIN);
__gpio_as_func0(RD_N_PIN);
__gpio_as_func0(WE_N_PIN);
reg = REG_EMC_SMCR3;
reg = (reg & (~EMC_SMCR_BW_MASK)) | EMC_SMCR_BW_16BIT;
REG_EMC_SMCR3 = reg;
dev->iobase = 0xac000000;
#endif // !defined(CONFIG_AQUILA)
#endif
sprintf(dev->name, "JZ ETHERNET");
dev->priv = 0;
dev->init = jz_eth_init;
dev->halt = jz_eth_halt;
dev->send = jz_eth_send;
dev->recv = jz_eth_rx;
eth_register(dev);
return 1;
}
int rtl8139_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
/* Find RTL8139 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
if (!dev) {
printf("Can not allocate memory of rtl8139\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8139#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)bus_to_phys(iobase);
dev->init = rtl8139_probe;
dev->halt = rtl_disable;
dev->send = rtl_transmit;
dev->recv = rtl_poll;
#ifdef CONFIG_MCAST_TFTP
dev->mcast = rtl_bcast_addr;
#endif
eth_register (dev);
card_number++;
pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
udelay (10 * 1000);
}
return card_number;
}
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
struct eth_device *netdev;
macb = malloc(sizeof(struct macb_device));
if (!macb) {
printf("Error: Failed to allocate memory for MACB%d\n", id);
return -1;
}
memset(macb, 0, sizeof(struct macb_device));
netdev = &macb->netdev;
macb->regs = regs;
macb->phy_addr = phy_addr;
if (macb_is_gem(macb))
sprintf(netdev->name, "gmac%d", id);
else
sprintf(netdev->name, "macb%d", id);
netdev->init = macb_init;
netdev->halt = macb_halt;
netdev->send = macb_send;
netdev->recv = macb_recv;
netdev->write_hwaddr = macb_write_hwaddr;
_macb_eth_initialize(macb);
eth_register(netdev);
#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
mdiodev->read = macb_miiphy_read;
mdiodev->write = macb_miiphy_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
macb->bus = miiphy_get_dev_by_name(netdev->name);
#endif
return 0;
}
/***********************************************************
* mvEgigaLoad -- *
* load a network interface into uboot network core. *
* initialize sw structures e.g. private, rings, etc. *
***********************************************************/
static int mvEgigaLoad(int port, char *name, char *enet_addr)
{
struct eth_device *dev = NULL;
egigaPriv *priv = NULL;
/* First disable GMAC */
mvGmacPortDisable(port);
dev = malloc(sizeof(struct eth_device));
if (!dev) {
printf("%s: %s falied to alloc eth_device (error)\n", __func__, name);
goto error;
}
priv = malloc(sizeof(egigaPriv));
if (!priv) {
printf("%s: %s falied to alloc egiga_priv (error)\n", __func__, name);
goto error;
}
memset(priv, 0, sizeof(egigaPriv));
/* init device methods */
memcpy(dev->name, name, NAMESIZE);
mvMacStrToHex(enet_addr, (MV_U8 *)(dev->enetaddr));
dev->init = (void *)mvEgigaInit;
dev->halt = (void *)mvEgigaHalt;
dev->send = (void *)mvEgigaTx;
dev->recv = (void *)mvEgigaRx;
dev->priv = priv;
dev->iobase = 0;
dev->write_hwaddr = 0;
priv->port = port;
priv->devInit = MV_FALSE;
priv->devEnable = MV_FALSE;
/* register the interface */
eth_register(dev);
return 0;
error:
printf("%s: %s load failed\n", __func__, name);
if (priv)
free(dev->priv);
if (dev)
free(dev);
return -1;
}
int mpc82xx_scc_enet_initialize(bd_t *bis)
{
struct eth_device *dev;
dev = (struct eth_device *) malloc(sizeof *dev);
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "SCC");
dev->init = sec_init;
dev->halt = sec_halt;
dev->send = sec_send;
dev->recv = sec_rx;
eth_register(dev);
return 1;
}
int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
unsigned long dma_addr)
{
struct eth_device *dev;
struct axidma_priv *priv;
dev = calloc(1, sizeof(struct eth_device));
if (dev == NULL)
return -1;
dev->priv = calloc(1, sizeof(struct axidma_priv));
if (dev->priv == NULL) {
free(dev);
return -1;
}
priv = dev->priv;
sprintf(dev->name, "aximac.%lx", base_addr);
dev->iobase = base_addr;
priv->dmatx = (struct axidma_reg *)dma_addr;
/* RX channel offset is 0x30 */
priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30);
dev->init = axiemac_init;
dev->halt = axiemac_halt;
dev->send = axiemac_send;
dev->recv = axiemac_recv;
dev->write_hwaddr = axiemac_setup_mac;
#ifdef CONFIG_PHY_ADDR
priv->phyaddr = CONFIG_PHY_ADDR;
#else
priv->phyaddr = -1;
#endif
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write);
priv->bus = miiphy_get_dev_by_name(dev->name);
priv->bus->reset = axiemac_bus_reset;
#endif
return 1;
}
