static int ethoc_write_hwaddr_common(struct ethoc *priv, u8 *mac)
{
ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
(mac[4] << 8) | (mac[5] << 0));
ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
return 0;
}
static int ethoc_reset(struct eth_device *dev)
{
u32 mode;
/* todo: reset controller? */
ethoc_disable_rx_and_tx(dev);
/* todo: setup registers */
/* enable fcs generation and automatic padding */
mode = ethoc_read(dev, MODER);
mode |= MODER_CRC | MODER_PAD;
ethoc_write(dev, MODER, mode);
/* set full-duplex mode */
mode = ethoc_read(dev, MODER);
mode |= MODER_FULLD;
ethoc_write(dev, MODER, mode);
ethoc_write(dev, IPGT, 0x15);
mode = ethoc_read(dev, CTRLMODER);
mode |= (1<<2) | 1;
ethoc_write(dev, CTRLMODER, mode); // text interrupt enable
// ethoc_write(dev, CTRLMODER, 2); // recv interrupt enable
//ethoc_ack_irq(dev, int_mask_all);
ethoc_ack_irq(dev, INT_MASK_ALL);
ethoc_enable_rx_and_tx(dev);
return 0;
}
static int ethoc_reset(struct ethoc *dev)
{
u32 mode;
/* TODO: reset controller? */
ethoc_disable_rx_and_tx(dev);
/* TODO: setup registers */
/* enable FCS generation and automatic padding */
mode = ethoc_read(dev, MODER);
mode |= MODER_CRC | MODER_PAD;
ethoc_write(dev, MODER, mode);
/* set full-duplex mode */
mode = ethoc_read(dev, MODER);
mode |= MODER_FULLD;
ethoc_write(dev, MODER, mode);
ethoc_write(dev, IPGT, 0x15);
ethoc_ack_irq(dev, INT_MASK_ALL);
ethoc_enable_irq(dev, INT_MASK_ALL);
ethoc_enable_rx_and_tx(dev);
return 0;
}
static inline void ethoc_write_bd(struct eth_device *dev, int index,
const struct ethoc_bd *bd)
{
loff_t offset = ethoc_bd_base + (index * sizeof(struct ethoc_bd));
ethoc_write(dev, offset + 0, bd->stat);
ethoc_write(dev, offset + 4, bd->addr);
}
static inline void ethoc_write_bd(struct ethoc *dev, int index,
const struct ethoc_bd *bd)
{
loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
ethoc_write(dev, offset + 0, bd->stat);
ethoc_write(dev, offset + 4, bd->addr);
}
static int ethoc_reset(struct ethoc *dev)
{
u32 mode;
/* */
ethoc_disable_rx_and_tx(dev);
/* */
/* */
mode = ethoc_read(dev, MODER);
mode |= MODER_CRC | MODER_PAD;
ethoc_write(dev, MODER, mode);
/* */
mode = ethoc_read(dev, MODER);
mode |= MODER_FULLD;
ethoc_write(dev, MODER, mode);
ethoc_write(dev, IPGT, 0x15);
ethoc_ack_irq(dev, INT_MASK_ALL);
ethoc_enable_irq(dev, INT_MASK_ALL);
ethoc_enable_rx_and_tx(dev);
return 0;
}
static int ethoc_set_mac_address(struct eth_device *dev)
{
u8 *mac = dev->enetaddr;
ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
(mac[4] << 8) | (mac[5] << 0));
ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
return 0;
}
static int ethoc_init(struct eth_device *dev)//, bd_t * bd)
{
struct ethoc *priv = (struct ethoc *)dev->priv;
//rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
//rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
priv->num_tx = 1;
priv->num_rx = pktbufsrx;
ethoc_write(dev, TX_BD_NUM/*tx_bd_num*/, priv->num_tx);
ethoc_init_ring(dev);
ethoc_reset(dev);
return 0;
}
static int ethoc_init(struct eth_device *dev, bd_t * bd)
{
struct ethoc *priv = (struct ethoc *)dev->priv;
printf("ethoc\n");
priv->num_tx = 1;
priv->num_rx = PKTBUFSRX;
ethoc_write(dev, TX_BD_NUM, priv->num_tx);
ethoc_init_ring(dev);
ethoc_reset(dev);
return 0;
}
static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
{
struct ethoc_bd bd;
int i;
void* vma;
dev->cur_tx = 0;
dev->dty_tx = 0;
dev->cur_rx = 0;
ethoc_write(dev, TX_BD_NUM, dev->num_tx);
/* setup transmission buffers */
bd.addr = mem_start;
bd.stat = TX_BD_IRQ | TX_BD_CRC;
vma = dev->membase;
for (i = 0; i < dev->num_tx; i++) {
if (i == dev->num_tx - 1)
bd.stat |= TX_BD_WRAP;
ethoc_write_bd(dev, i, &bd);
bd.addr += ETHOC_BUFSIZ;
dev->vma[i] = vma;
vma += ETHOC_BUFSIZ;
}
bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
for (i = 0; i < dev->num_rx; i++) {
if (i == dev->num_rx - 1)
bd.stat |= RX_BD_WRAP;
ethoc_write_bd(dev, dev->num_tx + i, &bd);
bd.addr += ETHOC_BUFSIZ;
dev->vma[dev->num_tx + i] = vma;
vma += ETHOC_BUFSIZ;
}
return 0;
}
static int ethoc_init_common(struct ethoc *priv)
{
int ret = 0;
priv->num_tx = 1;
priv->num_rx = PKTBUFSRX;
ethoc_write(priv, TX_BD_NUM, priv->num_tx);
ethoc_init_ring(priv);
ethoc_reset(priv);
#ifdef CONFIG_PHYLIB
ret = phy_startup(priv->phydev);
if (ret) {
printf("Could not initialize PHY %s\n",
priv->phydev->dev->name);
return ret;
}
#endif
return ret;
}
static int ethoc_init_ring(struct ethoc *dev)
{
struct ethoc_bd bd;
int i;
dev->num_tx = 1;
dev->num_rx = PKTBUFSRX;
dev->cur_tx = 0;
dev->dty_tx = 0;
dev->cur_rx = 0;
ethoc_write(dev, TX_BD_NUM, dev->num_tx);
/* setup transmission buffers */
bd.addr = 0;
bd.stat = TX_BD_IRQ | TX_BD_CRC;
for (i = 0; i < dev->num_tx; i++) {
if (i == dev->num_tx - 1)
bd.stat |= TX_BD_WRAP;
ethoc_write_bd(dev, i, &bd);
}
bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
for (i = 0; i < dev->num_rx; i++) {
if (i == dev->num_rx - 1)
bd.stat |= RX_BD_WRAP;
bd.addr = (u32)NetRxPackets[i];
ethoc_write_bd(dev, dev->num_tx + i, &bd);
flush_dcache_range(bd.addr, bd.addr + PKTSIZE);
}
return 0;
}
static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
{
u32 mode = ethoc_read(dev, MODER);
mode &= ~(MODER_RXEN | MODER_TXEN);
ethoc_write(dev, MODER, mode);
}
static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
{
ethoc_write(dev, INT_SOURCE, mask);
}
static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
{
u32 imask = ethoc_read(dev, INT_MASK);
imask &= ~mask;
ethoc_write(dev, INT_MASK, imask);
}
static void ethoc_enable_rx_and_tx(struct ethoc *dev)
{
u32 mode = ethoc_read(dev, MODER);
mode |= MODER_RXEN | MODER_TXEN;
ethoc_write(dev, MODER, mode);
}
static void ethoc_enable_irq(struct ethoc *dev, u32 mask)
{
u32 imask = ethoc_read(dev, INT_MASK);
imask |= mask;
ethoc_write(dev, INT_MASK, imask);
}
static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask)
{
//ethoc_write(dev, INT_SOURCE, 0x7f );
ethoc_write(dev, INT_SOURCE, mask/*1<<6*/);
}
static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
{
u32 mode = ethoc_read(priv, MODER);
mode |= MODER_RXEN | MODER_TXEN;
ethoc_write(priv, MODER, mode);
}
