void exar7250_stop_intr(struct channel *sc, u32 type) { exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE, 0); exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS); switch (type) { case SBE_2T3E3_FRAME_TYPE_E3_G751: case SBE_2T3E3_FRAME_TYPE_E3_G832: exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1, 0); exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2, 0); exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_CONTROL, 0); exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_CONTROL); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS, 0); exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS); break; case SBE_2T3E3_FRAME_TYPE_T3_CBIT: case SBE_2T3E3_FRAME_TYPE_T3_M13: exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE, 0); exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS, 0); exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL, 0); exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS, 0); exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS, 0); exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS); break; } }
void exar7250_init(struct channel *sc) { exar7250_write(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE, SBE_2T3E3_FRAMER_VAL_T3_CBIT | SBE_2T3E3_FRAMER_VAL_INTERRUPT_ENABLE_RESET | SBE_2T3E3_FRAMER_VAL_TIMING_ASYNCH_TXINCLK); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL, SBE_2T3E3_FRAMER_VAL_DISABLE_TX_LOSS_OF_CLOCK | SBE_2T3E3_FRAMER_VAL_DISABLE_RX_LOSS_OF_CLOCK | SBE_2T3E3_FRAMER_VAL_AMI_LINE_CODE | SBE_2T3E3_FRAMER_VAL_RX_LINE_CLOCK_INVERT); exar7250_set_frame_type(sc, SBE_2T3E3_FRAME_TYPE_T3_CBIT); }
void t3e3_reg_write(struct channel *sc, u32 *reg) { u32 i; switch (reg[0]) { case SBE_2T3E3_CHIP_21143: dc_write(sc->addr, reg[1], reg[2]); break; case SBE_2T3E3_CHIP_CPLD: for (i = 0; i < SBE_2T3E3_CPLD_REG_MAX; i++) if (cpld_reg_map[i][sc->h.slot] == reg[1]) { cpld_write(sc, i, reg[2]); break; } break; case SBE_2T3E3_CHIP_FRAMER: for (i = 0; i < SBE_2T3E3_FRAMER_REG_MAX; i++) if (t3e3_framer_reg_map[i] == reg[1]) { exar7250_write(sc, i, reg[2]); break; } break; case SBE_2T3E3_CHIP_LIU: for (i = 0; i < SBE_2T3E3_LIU_REG_MAX; i++) if (t3e3_liu_reg_map[i] == reg[1]) { exar7300_write(sc, i, reg[2]); break; } break; } }
void exar7250_set_frame_type(struct channel *sc, u32 type) { u32 val; switch (type) { case SBE_2T3E3_FRAME_TYPE_E3_G751: case SBE_2T3E3_FRAME_TYPE_E3_G832: case SBE_2T3E3_FRAME_TYPE_T3_CBIT: case SBE_2T3E3_FRAME_TYPE_T3_M13: break; default: return; } exar7250_stop_intr(sc, type); val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE); val &= ~(SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE | SBE_2T3E3_FRAMER_VAL_T3_E3_SELECT | SBE_2T3E3_FRAMER_VAL_FRAME_FORMAT_SELECT); switch (type) { case SBE_2T3E3_FRAME_TYPE_E3_G751: val |= SBE_2T3E3_FRAMER_VAL_E3_G751; break; case SBE_2T3E3_FRAME_TYPE_E3_G832: val |= SBE_2T3E3_FRAMER_VAL_E3_G832; break; case SBE_2T3E3_FRAME_TYPE_T3_CBIT: val |= SBE_2T3E3_FRAMER_VAL_T3_CBIT; break; case SBE_2T3E3_FRAME_TYPE_T3_M13: val |= SBE_2T3E3_FRAMER_VAL_T3_M13; break; default: return; } exar7250_write(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE, val); exar7250_start_intr(sc, type); }
void exar7250_start_intr(struct channel *sc, u32 type) { u32 val; switch (type) { case SBE_2T3E3_FRAME_TYPE_E3_G751: case SBE_2T3E3_FRAME_TYPE_E3_G832: val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2); #if 0 sc->s.LOS = val & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS ? 1 : 0; #else cpld_LOS_update(sc); #endif sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0; exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1, SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE | SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE); #if 0 /* */ #endif exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2); #if 0 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2, SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_ENABLE | SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_ENABLE | SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_ENABLE); #endif break; case SBE_2T3E3_FRAME_TYPE_T3_CBIT: case SBE_2T3E3_FRAME_TYPE_T3_M13: val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS); #if 0 sc->s.LOS = val & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS ? 1 : 0; #else cpld_LOS_update(sc); #endif sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0; exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE, SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE | SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE); #if 0 /* */ #endif exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS); #if 0 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS, SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_ENABLE | SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_ENABLE); #endif exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL, 0); break; default: return; } exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS); exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE, SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_ENABLE | SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_ENABLE); }