void
ia32(void)
{
int rv;
rv = sigsetjmp(exec_1step_jmpbuf, 1);
switch (rv) {
case 0:
break;
case 1:
VERBOSE(("ia32: return from exception"));
break;
case 2:
VERBOSE(("ia32: return from panic"));
return;
default:
VERBOSE(("ia32: return from unknown cause"));
break;
}
#if defined(IA32_SUPPORT_DEBUG_REGISTER)
do {
exec_1step();
if (dmac.working) {
dmax86();
}
} while (CPU_REMCLOCK > 0);
#else
if (CPU_TRAP) {
do {
exec_1step();
if (CPU_TRAP) {
CPU_DR6 |= CPU_DR6_BS;
INTERRUPT(1, TRUE, FALSE, 0);
}
dmax86();
} while (CPU_REMCLOCK > 0);
} else if (dmac.working) {
do {
exec_1step();
dmax86();
} while (CPU_REMCLOCK > 0);
} else {
do {
exec_1step();
} while (CPU_REMCLOCK > 0);
}
#endif
}
UINT8
ia32_step(void)
{
int rv;
rv = sigsetjmp(exec_1step_jmpbuf, 1);
switch (rv) {
case 0:
break;
case 1:
VERBOSE(("ia32_step: return from exception"));
break;
case 2:
VERBOSE(("ia32_step: return from panic"));
return FALSE;
default:
VERBOSE(("ia32_step: return from unknown cause"));
break;
}
// do {
exec_1step();
if (CPU_TRAP) {
CPU_DR6 |= CPU_DR6_BS;
INTERRUPT(1, INTR_TYPE_EXCEPTION);
}
if (dmac.working) {
dmax86();
}
// } while (CPU_REMCLOCK > 0);
return TRUE;
}
void
STI(void)
{
CPU_WORKCLOCK(2);
if (CPU_STAT_PM) {
if (!CPU_STAT_VM86) {
if (CPU_STAT_CPL > CPU_STAT_IOPL) {
EXCEPTION(GP_EXCEPTION, 0);
}
} else {
if (CPU_STAT_IOPL < 3) {
EXCEPTION(GP_EXCEPTION, 0);
}
}
}
CPU_FLAG |= I_FLAG;
CPU_TRAP = (CPU_FLAG & (I_FLAG|T_FLAG)) == (I_FLAG|T_FLAG);
exec_1step();
IRQCHECKTERM();
}
UINT8
ia32(void)
{
int rv;
rv = sigsetjmp(exec_1step_jmpbuf, 1);
switch (rv) {
case 0:
break;
case 1:
VERBOSE(("ia32: return from exception"));
break;
case 2:
VERBOSE(("ia32: return from panic"));
return FALSE;
default:
VERBOSE(("ia32: return from unknown cause"));
break;
}
do {
exec_1step();
if (CPU_TRAP) {
CPU_DR6 |= CPU_DR6_BS;
INTERRUPT(1, INTR_TYPE_EXCEPTION);
dmax86();
} else if (dmac.working) {
dmax86();
}
if(np2break_is_next()) {
return FALSE;
}
} while (CPU_REMCLOCK > 0 && !np2stopemulate);
return TRUE;
}
