void extcl_cpu_wr_mem_BMC411120C(WORD address, BYTE value) {
if (address >= 0x8000) {
BYTE old_prg_rom_cfg = mmc3.prg_rom_cfg;
BYTE old_chr_rom_cfg = mmc3.chr_rom_cfg;
switch (address & 0xE001) {
case 0x8000:
extcl_cpu_wr_mem_MMC3(address, value);
bmc411120c_8000()
bmc411120c_update_prg();
bmc411120c_update_chr();
return;
case 0x8001:
extcl_cpu_wr_mem_MMC3(address, value);
bmc411120c_8001()
bmc411120c_update_prg();
bmc411120c_update_chr();
return;
default:
extcl_cpu_wr_mem_MMC3(address, value);
return;
}
}
if ((address >= 0x6000) && (address <= 0x7FFF)) {
bmc411120c.reg = address & 0xFF;
bmc411120c_update_prg();
bmc411120c_update_chr();
}
}
void extcl_cpu_wr_mem_217(WORD address, BYTE value) {
if (address > 0x7FFF) {
switch (address & 0xE001) {
case 0x8000:
if (!m217.reg[2]) {
m217_8000()
} else {
extcl_cpu_wr_mem_MMC3(0xC000, value);
}
return;
case 0x8001: {
if (!m217.reg[2]) {
m217_8001()
} else {
static const BYTE security[8] = { 0, 6, 3, 7, 5, 2, 4, 1};
BYTE save = value;
m217.reg[3] = TRUE;
value = (save & 0xC0) | security[save & 0x07];
m217_8000()
}
return;
}
case 0xA000:
if (!m217.reg[2]) {
if (value & 0x01) {
mirroring_H();
} else {
mirroring_V();
}
} else {
if (m217.reg[3] && (!(m217.reg[0] & 0x80) || (mmc3.bank_to_update < 6))) {
m217.reg[3] = FALSE;
m217_8001()
}
}
return;
case 0xA001:
if (!m217.reg[2]) {
extcl_cpu_wr_mem_MMC3(address, value);
} else {
if (value & 0x01) {
mirroring_H();
} else {
mirroring_V();
}
}
return;
}
extcl_cpu_wr_mem_MMC3(address, value);
return;
}
void extcl_cpu_wr_mem_254(WORD address, BYTE value) {
if (address == 0x8000) {
m254.reg[0] = 0xFF;
} else if (address == 0xA001) {
m254.reg[1] = value;
}
extcl_cpu_wr_mem_MMC3(address, value);
}
void extcl_cpu_wr_mem_182(WORD address, BYTE value) {
switch (address & 0xE001) {
case 0x8001:
extcl_cpu_wr_mem_MMC3(0xA000, value);
return;
case 0xA000:
extcl_cpu_wr_mem_MMC3(0x8000, value);
return;
case 0xC000: {
switch (mmc3.bank_to_update) {
case 0: {
DBWORD bank;
value >>= 1;
control_bank(info.chr.rom[0].max.banks_2k)
bank = value << 11;
chr.bank_1k[mmc3.chr_rom_cfg] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[mmc3.chr_rom_cfg | 0x01] = chr_chip_byte_pnt(0, bank | 0x0400);
break;
}
case 1:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[(mmc3.chr_rom_cfg ^ 0x04) | 0x01] = chr_chip_byte_pnt(0, value << 10);
break;
case 2: {
DBWORD bank;
value >>= 1;
control_bank(info.chr.rom[0].max.banks_2k)
bank = value << 11;
chr.bank_1k[mmc3.chr_rom_cfg | 0x02] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[mmc3.chr_rom_cfg | 0x03] = chr_chip_byte_pnt(0, bank | 0x0400);
break;
}
case 3:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[(mmc3.chr_rom_cfg ^ 0x04) | 0x03] = chr_chip_byte_pnt(0, value << 10);
break;
case 4:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, mmc3.prg_rom_cfg, value);
map_prg_rom_8k_update();
break;
case 5:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 1, value);
map_prg_rom_8k_update();
break;
case 6:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[mmc3.chr_rom_cfg ^ 0x04] = chr_chip_byte_pnt(0, value << 10);
break;
case 7:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[(mmc3.chr_rom_cfg ^ 0x04) | 0x02] = chr_chip_byte_pnt(0, value << 10);
break;
}
return;
}
case 0xC001:
irqA12.latch = value;
irqA12.reload = TRUE;
irqA12.counter = 0;
return;
case 0xE000:
case 0xE001:
extcl_cpu_wr_mem_MMC3(address, value);
return;
}
}
void extcl_cpu_wr_mem_SL1632(WORD address, BYTE value) {
if (address < 0x4100) {
return;
}
if (address == 0xA131) {
if (sl1632.mode != value) {
sl1632.mode = value;
if (value & 0x02) {
sl1632_update_mmc3();
} else {
sl1632_update();
}
}
}
if (sl1632.mode & 0x02) {
BYTE old_prg_rom_cfg = mmc3.prg_rom_cfg;
BYTE old_chr_rom_cfg = mmc3.chr_rom_cfg;
switch (address & 0xF001) {
case 0x8000:
extcl_cpu_wr_mem_MMC3(address, value);
sl1632_8000_mmc3()
sl1632_update_chr_mmc3();
return;
case 0x8001:
extcl_cpu_wr_mem_MMC3(address, value);
sl1632_8001_mmc3()
sl1632_update_chr_mmc3();
return;
case 0xA000:
extcl_cpu_wr_mem_MMC3(address, value);
sl1632.mmc3.mirroring = value & 0x01;
return;
default:
extcl_cpu_wr_mem_MMC3(address, value);
return;
}
} else {
WORD tmp;
switch (address & 0xF003) {
case 0x8000:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 0, value);
map_prg_rom_8k_update();
sl1632.prg_map[0] = value;
return;
case 0x9000:
sl1632.mirroring = value & 0x01;
sl1632_mirroring(sl1632.mirroring)
return;
case 0xA000:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 1, value);
map_prg_rom_8k_update();
sl1632.prg_map[1] = value;
return;
case 0xB000:
sl1632_chr_1k_ns(0);
return;
case 0xB001:
sl1632_chr_1k_4s(0);
return;
case 0xB002:
sl1632_chr_1k_ns(1);
return;
case 0xB003:
sl1632_chr_1k_4s(1);
return;
case 0xC000:
sl1632_chr_1k_ns(2);
return;
case 0xC001:
sl1632_chr_1k_4s(2);
return;
case 0xC002:
sl1632_chr_1k_ns(3);
return;
case 0xC003:
sl1632_chr_1k_4s(3);
return;
case 0xD000:
sl1632_chr_1k_ns(4);
return;
case 0xD001:
sl1632_chr_1k_4s(4);
return;
case 0xD002:
sl1632_chr_1k_ns(5);
return;
case 0xD003:
sl1632_chr_1k_4s(5);
return;
case 0xE000:
sl1632_chr_1k_ns(6);
return;
case 0xE001:
sl1632_chr_1k_4s(6);
return;
case 0xE002:
sl1632_chr_1k_ns(7);
return;
case 0xE003:
sl1632_chr_1k_4s(7);
return;
}
}
}
void extcl_cpu_wr_mem_121(WORD address, BYTE value) {
if (address >= 0x8000) {
const BYTE prg_rom_cfg = (value & 0x40) >> 5;
extcl_cpu_wr_mem_MMC3(address, value);
switch (address & 0xE003) {
case 0x8000: {
if (mmc3.prg_rom_cfg != prg_rom_cfg) {
mapper.rom_map_to[2] = m121.bck[0];
mapper.rom_map_to[0] = m121.bck[1];
m121.bck[0] = mapper.rom_map_to[0];
m121.bck[1] = mapper.rom_map_to[2];
}
m121_swap_8k_prg();
break;
}
case 0x8001:
if (mmc3.bank_to_update == 6) {
if (mmc3.prg_rom_cfg) {
control_bank(info.prg.rom.max.banks_8k)
m121.bck[1] = value;
} else {
control_bank(info.prg.rom.max.banks_8k)
m121.bck[0] = value;
}
}
m121_swap_8k_prg();
break;
case 0x8003:
switch (value) {
case 0x20:
m121.reg[1] = 0x13;
break;
case 0x29:
m121.reg[1] = 0x1B;
break;
case 0x28:
m121.reg[0] = 0x0C;
break;
case 0x26:
m121.reg[1] = 0x08;
break;
case 0xAB:
m121.reg[1] = 0x07;
break;
case 0xEC:
case 0xEF:
m121.reg[1] = 0x0D;
break;
case 0xFF:
m121.reg[1] = 0x09;
break;
default:
m121.reg[0] = m121.reg[1] = 0;
break;
}
m121_swap_8k_prg();
break;
}
return;
}
if ((address < 0x5000) || (address > 0x5FFF)) {
return;
}
m121.reg[2] = vlu121[value & 0x03];
return;
}
