static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
struct clk *otg_clk;
u32 rstcon;
u32 phypwr;
int err = 0;
otg_clk = clk_get(&pdev->dev, "usbotg");
if (IS_ERR(otg_clk)) {
dev_err(&pdev->dev, "Failed to get otg clock\n");
return PTR_ERR(otg_clk);
}
err = clk_enable(otg_clk);
if (err) {
clk_put(otg_clk);
return err;
}
if (exynos4_usb_host_phy_is_on()) {
/* set to resume HSIC 0 and 1 and standard of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND);
} else {
/* USB MUX change from Device to Host */
if (!exynos4_usb_device_phy_is_on())
exynos_usb_mux_change(pdev, 1);
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND);
}
writel(phypwr, EXYNOS4_PHYPWR);
err = 0;
} else {
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
exynos4_usb_phy_control(USB_PHY1, PHY_ENABLE);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
exynos4_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* USB MUX change from Device to Host */
if (!exynos4_usb_device_phy_is_on())
exynos_usb_mux_change(pdev, 1);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
err = 1;
}
udelay(80);
clk_disable(otg_clk);
clk_put(otg_clk);
return err;
}
static int exynos4_check_usb_op(void)
{
u32 phypwr;
u32 op = 1;
unsigned long flags;
int ret;
#if defined(CONFIG_MDM_HSIC_PM)
/* if it is normal boot, block lpa till modem boot */
if (set_hsic_lpa_states(STATE_HSIC_LPA_CHECK))
return 1;
#endif
ret = clk_enable(phy_clk);
if (ret)
return 0;
local_irq_save(flags);
phypwr = readl(EXYNOS4_PHYPWR);
/*If USB Device is power on, */
if (exynos4_usb_device_phy_is_on()) {
op = 1;
goto done;
} else if (!exynos4_usb_host_phy_is_on()) {
op = 0;
goto done;
}
/*If USB Device & Host is suspended, */
if (soc_is_exynos4210()) {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* HSIC LPA: LPA USB phy retention reume call the usb
* reset resume, so we should let CP to HSIC L3 mode. */
set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
#endif
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
writel(PHY_DISABLE, S5P_USBHOST_PHY_CONTROL);
op = 0;
}
} else {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND)) {
#if 0
if( USB_PHY_L3 == usb_phy_control.status)
return;
#ifdef CONFIG_SMM6260_MODEM//diog.zhao 120605
smm6260_set_active_state(0);
#endif
/* unset to normal of Host */
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN
| EXYNOS4212_HSIC0_ANALOG_POWERDOWN
| EXYNOS4212_HSIC1_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
/* unset to normal of Device */
writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
usb_phy_control.status = USB_PHY_L3;
#endif
op = 0;
usb_phy_control.lpa_entered = 1;
}
}
done:
local_irq_restore(flags);
clk_disable(phy_clk);
return op;
}
int exynos4_check_usb_op(void)
{
static struct clk *otg_clk;
unsigned long flags;
u32 phypwr;
u32 op = 1;
if (!otg_clk) {
otg_clk = clk_get(NULL, "usbotg");
if (IS_ERR(otg_clk)) {
printk(KERN_ERR"Failed to get otg clock\n");
otg_clk = NULL;
return 0;
}
}
clk_enable(otg_clk);
local_irq_save(flags);
phypwr = readl(EXYNOS4_PHYPWR);
/*If USB Device is power on, */
if (exynos4_usb_device_phy_is_on()) {
op = 1;
goto done;
} else if (!exynos4_usb_host_phy_is_on()) {
op = 0;
goto done;
}
/*If USB Device & Host is suspended, */
if (soc_is_exynos4210()) {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
exynos4_usb_phy_control(USB_PHY1, PHY_DISABLE);
op = 0;
}
} else {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND)) {
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN
| EXYNOS4212_HSIC0_ANALOG_POWERDOWN
| EXYNOS4212_HSIC1_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
exynos4_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
op = 0;
}
}
done:
local_irq_restore(flags);
clk_disable(otg_clk);
return op;
}
static int exynos4_check_usb_op(void)
{
u32 phypwr;
u32 op = 1;
unsigned long flags;
int ret;
ret = clk_enable(phy_clk);
if (ret)
return 0;
local_irq_save(flags);
phypwr = readl(EXYNOS4_PHYPWR);
/*If USB Device is power on, */
if (exynos4_usb_device_phy_is_on()) {
op = 1;
goto done;
} else if (!exynos4_usb_host_phy_is_on()) {
op = 0;
goto done;
}
/*If USB Device & Host is suspended, */
if (soc_is_exynos4210()) {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
writel(PHY_DISABLE, S5P_USBHOST_PHY_CONTROL);
op = 0;
}
} else {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4X12_HSIC0_FORCE_SUSPEND
| EXYNOS4X12_HSIC1_FORCE_SUSPEND)) {
/* unset to normal of Host */
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN
| EXYNOS4X12_HSIC0_ANALOG_POWERDOWN
| EXYNOS4X12_HSIC1_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
/* unset to normal of Device */
writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
op = 0;
usb_phy_control.lpa_entered = 1;
}
}
done:
local_irq_restore(flags);
clk_disable(phy_clk);
return op;
}
