static int exynos4_usb_phy1_exit(struct platform_device *pdev)
{
u32 phypwr;
if (!strcmp(pdev->name, "s5p-ehci"))
clear_bit(HOST_PHY_EHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s5p-ohci"))
clear_bit(HOST_PHY_OHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s3c-usbgadget"))
clear_bit(HOST_PHY_DEVICE, &usb_phy_control.usage);
if (usb_phy_control.usage) {
dev_info(&pdev->dev, "still being used(%ld)\n",usb_phy_control.usage);
return -EBUSY;
}
phypwr = readl(EXYNOS4_PHYPWR)
| PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY1, PHY_DISABLE);
return 0;
}
static int exynos4_usb_phy20_exit(struct platform_device *pdev)
{
u32 phypwr;
if (atomic_dec_return(&host_usage) > 0) {
dev_info(&pdev->dev, "still being used\n");
return -EBUSY;
}
/* unset to normal of Device */
writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
EXYNOS4_PHYPWR);
/* unset to normal of Host */
phypwr = readl(EXYNOS4_PHYPWR)
| PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
usb_phy_control.lpa_entered = 0;
return 0;
}
static int exynos5_usb_phy20_exit(struct platform_device *pdev)
{
u32 hostphy_ctrl0, otgphy_sys, hsic_ctrl;
if (atomic_dec_return(&host_usage) > 0) {
dev_info(&pdev->dev, "still being used\n");
return -EBUSY;
}
hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |
HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP | HSIC_CTRL_FORCESUSPEND);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
hostphy_ctrl0 |= (HOST_CTRL0_SIDDQ);
hostphy_ctrl0 |= (HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
hostphy_ctrl0 |= (HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL);
writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
otgphy_sys |= (OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG | OTG_SYS_FORCE_SLEEP);
writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
exynos_usb_phy_control(USB_PHY1, PHY_DISABLE);
return 0;
}
static int __maybe_unused exynos_usb_hsic_init(struct platform_device *pdev)
{
u32 rstcon, hsic_ctrl;
if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos_usb_phy_control(USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* reset both PHY and Link of Host */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_PHY1_HSIC0_SWRST
| EXYNOS4212_PHY1_HSIC1_SWRST;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_PHY1_HSIC0_SWRST
| EXYNOS4212_PHY1_HSIC1_SWRST);
writel(rstcon, EXYNOS4_RSTCON);
} else {
/* HSIC phy reset */
hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |
HSIC_CTRL_PHYSWRST);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
udelay(10);
hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
}
return 0;
}
static int exynos4_usb_phy0_init(struct platform_device *pdev)
{
u32 phypwr;
u32 phyclk;
u32 rstcon;
exynos_usb_phy_control(USB_PHY0, PHY_ENABLE);
/* set clock frequency for PLL */
phyclk = readl(EXYNOS4_PHYCLK) & ~(EXYNOS4210_CLKSEL_MASK);
phyclk |= exynos_usb_phy_set_clock(pdev);
phyclk &= ~(PHY0_COMMON_ON_N);
writel(phyclk, EXYNOS4_PHYCLK);
/* set to normal of PHY0 */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
return 0;
}
static int exynos4_usb_phy0_exit(struct platform_device *pdev)
{
/* unset to normal of PHY0 */
writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY0, PHY_DISABLE);
return 0;
}
static int exynos4_usb_phy1_init(struct platform_device *pdev)
{
u32 phypwr;
u32 phyclk;
u32 rstcon;
atomic_inc(&host_usage);
if (exynos4_usb_host_phy_is_on()) {
dev_err(&pdev->dev, "Already power on PHY\n");
return 0;
}
/*
* set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
* 0x0 : pull-up/down disabled
* 0x1 : pull-down enabled
* 0x2 : reserved
* 0x3 : pull-up enabled
*/
writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
ETC6PUD);
exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
/* set clock frequency for PLL */
phyclk = exynos_usb_phy_set_clock(pdev);
phyclk &= ~(PHY1_COMMON_ON_N);
writel(phyclk, EXYNOS4_PHYCLK);
/* set to normal HSIC 0 and 1 of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* floating prevention logic: disable */
writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
udelay(80);
return 0;
}
static int exynos5_usb_phy30_exit(struct platform_device *pdev)
{
u32 reg;
reg = EXYNOS_USB3_PHYUTMI_OTGDISABLE |
EXYNOS_USB3_PHYUTMI_FORCESUSPEND |
EXYNOS_USB3_PHYUTMI_FORCESLEEP;
writel(reg, EXYNOS_USB3_PHYUTMI);
exynos_usb_phy_control(USB_PHY0, PHY_DISABLE);
return 0;
}
static int exynos5_check_usb_op(void)
{
u32 hostphy_ctrl0, otgphy_sys;
u32 op = 1;
unsigned long flags;
int ret;
ret = clk_enable(phy_clk);
if (ret)
return 0;
local_irq_save(flags);
/* Check USB 3.0 DRD power */
if (exynos5_usb_phy30_is_on()) {
op = 1;
goto done;
}
/*If USB Device is power on, */
if (exynos_usb_device_phy_is_on()) {
op = 1;
goto done;
} else if (!exynos5_usb_host_phy20_is_on()) {
op = 0;
goto done;
}
hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
if (hostphy_ctrl0 & HOST_CTRL0_FORCESUSPEND) {
/* unset to normal of Host */
hostphy_ctrl0 |= (HOST_CTRL0_SIDDQ);
writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
/* unset to normal of Device */
otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
otgphy_sys |= OTG_SYS_SIDDQ_UOTG;
writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
exynos_usb_phy_control(USB_PHY1,
PHY_DISABLE);
op = 0;
usb_phy_control.lpa_entered = 1;
}
done:
local_irq_restore(flags);
clk_disable(phy_clk);
return op;
}
static int exynos5_usb_phy30_init(struct platform_device *pdev)
{
u32 reg;
exynos_usb_phy_control(USB_PHY0, PHY_ENABLE);
/* Reset USB 3.0 PHY */
writel(0x087fffc0, EXYNOS_USB3_LINKSYSTEM);
writel(0x00000000, EXYNOS_USB3_PHYREG0);
writel(0x24d4e6e4, EXYNOS_USB3_PHYPARAM0);
writel(0x03fff820, EXYNOS_USB3_PHYPARAM1);
writel(0x00000000, EXYNOS_USB3_PHYBATCHG);
writel(0x00000000, EXYNOS_USB3_PHYRESUME);
/* REVISIT : Over-current pin is inactive on SMDK5250 */
if (soc_is_exynos5250())
writel((readl(EXYNOS_USB3_LINKPORT) & ~(0x3<<4)) |
(0x3<<2), EXYNOS_USB3_LINKPORT);
/* UTMI Power Control */
writel(EXYNOS_USB3_PHYUTMI_OTGDISABLE, EXYNOS_USB3_PHYUTMI);
/* Set 100MHz external clock */
reg = EXYNOS_USB3_PHYCLKRST_PORTRESET |
/* HS PLL uses ref_pad_clk{p,m} or ref_alt_clk_{p,m}
* as reference */
EXYNOS_USB3_PHYCLKRST_REFCLKSEL(2) |
/* Digital power supply in normal operating mode */
EXYNOS_USB3_PHYCLKRST_RETENABLEN |
/* 0x27-100MHz, 0x2a-24MHz, 0x31-20MHz, 0x38-19.2MHz */
EXYNOS_USB3_PHYCLKRST_FSEL(0x27) |
/* 0x19-100MHz, 0x68-24MHz, 0x7d-20Mhz */
EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x19) |
/* Enable ref clock for SS function */
EXYNOS_USB3_PHYCLKRST_REF_SSP_EN |
/* Enable spread spectrum */
EXYNOS_USB3_PHYCLKRST_SSC_EN;
writel(reg, EXYNOS_USB3_PHYCLKRST);
udelay(10);
reg &= ~(EXYNOS_USB3_PHYCLKRST_PORTRESET);
writel(reg, EXYNOS_USB3_PHYCLKRST);
return 0;
}
static int __maybe_unused exynos_usb_hsic_exit(struct platform_device *pdev)
{
u32 hsic_ctrl;
if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos_usb_phy_control(USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
} else {
hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |
HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP | HSIC_CTRL_FORCESUSPEND);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
}
return 0;
}
static int exynos5_usb_phy30_exit(struct platform_device *pdev)
{
u32 reg;
reg = EXYNOS_USB3_PHYUTMI_OTGDISABLE |
EXYNOS_USB3_PHYUTMI_FORCESUSPEND |
EXYNOS_USB3_PHYUTMI_FORCESLEEP;
writel(reg, EXYNOS_USB3_PHYUTMI);
/* Control PHYTEST to remove leakage current */
reg = readl(EXYNOS_USB3_PHYTEST);
reg |= (EXYNOS_USB3_PHYTEST_POWERDOWN_SSP |
EXYNOS_USB3_PHYTEST_POWERDOWN_HSP);
writel(reg, EXYNOS_USB3_PHYTEST);
exynos_usb_phy_control(USB_PHY0, PHY_DISABLE);
return 0;
}
static int exynos4_usb_phy1_exit(struct platform_device *pdev)
{
u32 phypwr;
if (atomic_dec_return(&host_usage) > 0) {
dev_info(&pdev->dev, "still being used\n");
return -EBUSY;
}
phypwr = readl(EXYNOS4_PHYPWR)
| PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY1, PHY_DISABLE);
return 0;
}
static int exynos4_usb_phy20_exit(struct platform_device *pdev)
{
u32 phypwr;
if (!strcmp(pdev->name, "s5p-ehci"))
clear_bit(HOST_PHY_EHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s5p-ohci"))
clear_bit(HOST_PHY_OHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s3c-usbgadget"))
clear_bit(HOST_PHY_DEVICE, &usb_phy_control.usage);
if (usb_phy_control.usage) {
dev_info(&pdev->dev, "still being used(%ld)\n",
usb_phy_control.usage);
return -EBUSY;
} else
dev_info(&pdev->dev, "usb host phy off\n");
/* unset to normal of Device */
writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
EXYNOS4_PHYPWR);
/* unset to normal of Host */
phypwr = readl(EXYNOS4_PHYPWR)
| PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
usb_phy_control.lpa_entered = 0;
return 0;
}
static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
u32 rstcon;
u32 phypwr;
int err;
if (exynos4_usb_host_phy_is_on()) {
/* set to resume HSIC 0 and 1 and standard of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND);
} else {
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND);
}
writel(phypwr, EXYNOS4_PHYPWR);
if (usb_phy_control.lpa_entered) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \
|| defined(CONFIG_MDM_HSIC_PM)
if (!strcmp(pdev->name, "s5p-ehci"))
set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
#endif
usb_phy_control.lpa_entered = 0;
err = 1;
} else {
err = 0;
}
} else {
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* set to normal of Host */
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \
|| defined(CONFIG_MDM_HSIC_PM)
if (!strcmp(pdev->name, "s5p-ehci"))
set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
#endif
usb_phy_control.lpa_entered = 0;
err = 1;
}
udelay(80);
return err;
}
int exynos4_check_usb_op(void)
{
u32 phypwr;
u32 op = 1;
unsigned long flags;
int ret;
ret = clk_enable(phy_clk);
if (ret)
return 0;
local_irq_save(flags);
phypwr = readl(EXYNOS4_PHYPWR);
/*If USB Device is power on, */
if (exynos_usb_device_phy_is_on()) {
op = 1;
goto done;
} else if (!exynos4_usb_host_phy_is_on()) {
op = 0;
goto done;
}
/*If USB Device & Host is suspended, */
if (soc_is_exynos4210()) {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* HSIC LPA: LPA USB phy retention reume call the usb
* reset resume, so we should let CP to HSIC L3 mode. */
set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
#endif
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
writel(PHY_DISABLE, S5P_USBHOST_PHY_CONTROL);
op = 0;
}
} else {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND)) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* HSIC LPA: LPA USB phy retention reume call the usb
* reset resume, so we should let CP to HSIC L3 mode. */
set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
#endif
/* unset to normal of Host */
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN
| EXYNOS4212_HSIC0_ANALOG_POWERDOWN
| EXYNOS4212_HSIC1_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
/* unset to normal of Device */
writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
op = 0;
usb_phy_control.lpa_entered = 1;
}
}
done:
local_irq_restore(flags);
clk_disable(phy_clk);
return op;
}
static int exynos4_usb_phy20_init(struct platform_device *pdev)
{
u32 phypwr, phyclk, rstcon;
//printk("[exynos4_usb_phy20_init]++++++++++++++\n");
atomic_inc(&host_usage);
if (exynos4_usb_phy20_is_on()) {
//dev_err(&pdev->dev, "Already power on PHY\n");
/*diog.zhao,0614,remove*/
//if(USB_PHY_L2 == usb_phy_control.status)
//return -1;
return 0;
}
if(USB_PHY_L0 == usb_phy_control.status)
return 0;
/*
* set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
* 0x0 : pull-up/down disabled
* 0x1 : pull-down enabled
* 0x2 : reserved
* 0x3 : pull-up enabled
*/
writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
ETC6PUD);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* USB MUX change from Device to Host */
exynos_usb_mux_change(pdev, 1);
/* set clock frequency for PLL */
phyclk = exynos_usb_phy_set_clock(pdev);
/* COMMON Block configuration during suspend */
phyclk &= ~(PHY0_COMMON_ON_N | PHY1_COMMON_ON_N);
writel(phyclk, EXYNOS4_PHYCLK);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* set to normal of Host */
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* reset both PHY and Link of Host */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
udelay(80);
usb_phy_control.status = USB_PHY_L0;
return 0;
}
static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
u32 rstcon;
u32 phypwr;
int err;
if (exynos4_usb_host_phy_is_on()) {
/* set to resume HSIC 0 and 1 and standard of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND);
} else {
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND);
}
writel(phypwr, EXYNOS4_PHYPWR);
if (usb_phy_control.lpa_entered) {
usb_phy_control.lpa_entered = 0;
err = 1;
} else
err = 0;
} else {
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* set to normal of Host */
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
usb_phy_control.lpa_entered = 0;
err = 1;
}
udelay(80);
return err;
}
static int exynos5_usb_phy20_init(struct platform_device *pdev)
{
u32 refclk_freq;
u32 hostphy_ctrl0, otgphy_sys, hsic_ctrl, ehcictrl, ohcictrl;
atomic_inc(&host_usage);
if (exynos5_usb_host_phy20_is_on()) {
dev_err(&pdev->dev, "Already power on PHY\n");
return 0;
}
exynos_usb_mux_change(pdev, 1);
exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
/* Host and Device should be set at the same time */
hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK);
otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
otgphy_sys &= ~(OTG_SYS_CTRL0_FSEL_MASK);
/* 2.0 phy reference clock configuration */
refclk_freq = exynos_usb_phy_set_clock(pdev);
hostphy_ctrl0 |= (refclk_freq << HOST_CTRL0_CLKSEL_SHIFT);
otgphy_sys |= (refclk_freq << OTG_SYS_CLKSEL_SHIFT);
/* COMMON Block configuration during suspend */
hostphy_ctrl0 |= HOST_CTRL0_COMMONON_N;
otgphy_sys &= ~(OTG_SYS_COMMON_ON);
/* otg phy reset */
otgphy_sys &= ~(OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG | OTG_SYS_FORCE_SLEEP);
otgphy_sys &= ~(OTG_SYS_REF_CLK_SEL_MASK);
otgphy_sys |= (OTG_SYS_REF_CLK_SEL(0x2) | OTG_SYS_OTGDISABLE);
otgphy_sys |= (OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG | OTG_SYS_PHYLINK_SW_RESET);
writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
udelay(10);
otgphy_sys &= ~(OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG | OTG_SYS_PHYLINK_SW_RESET);
writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
/* host phy reset */
hostphy_ctrl0 &= ~(HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL | HOST_CTRL0_SIDDQ);
hostphy_ctrl0 &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
hostphy_ctrl0 |= (HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
udelay(10);
hostphy_ctrl0 &= ~(HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
/* HSIC phy reset */
hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |
HSIC_CTRL_PHYSWRST);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
udelay(10);
hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
udelay(80);
/* enable EHCI DMA burst */
ehcictrl = readl(EXYNOS5_PHY_HOST_EHCICTRL);
ehcictrl |= (EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4 |
EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16);
writel(ehcictrl, EXYNOS5_PHY_HOST_EHCICTRL);
/* set ohci_suspend_on_n */
ohcictrl = readl(EXYNOS5_PHY_HOST_OHCICTRL);
ohcictrl |= OHCICTRL_SUSPLGCY;
writel(ohcictrl, EXYNOS5_PHY_HOST_OHCICTRL);
return 0;
}
static int exynos5_usb_phy_host_resume(struct platform_device *pdev)
{
u32 hostphy_ctrl0, otgphy_sys, hsic_ctrl;
int err;
if (exynos5_usb_host_phy20_is_on()) {
/* set to suspend HSIC 0 and 1 and standard of PHY1 */
hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
hostphy_ctrl0 &= ~(HOST_CTRL0_FORCESUSPEND);
writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
/* set common_on_n of PHY1 for power consumption */
hsic_ctrl = readl(EXYNOS5_PHY_HSIC_CTRL1);
hsic_ctrl &= ~(HSIC_CTRL_FORCESUSPEND);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
if (usb_phy_control.lpa_entered) {
usb_phy_control.lpa_entered = 0;
err = 1;
} else
err = 0;
} else {
exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
/* otg phy reset */
otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS);
otgphy_sys &= ~(OTG_SYS_SIDDQ_UOTG);
otgphy_sys |= (OTG_SYS_PHY0_SW_RST |
OTG_SYS_LINK_SW_RST_UOTG |
OTG_SYS_PHYLINK_SW_RESET);
writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
udelay(10);
otgphy_sys &= ~(OTG_SYS_PHY0_SW_RST |
OTG_SYS_LINK_SW_RST_UOTG |
OTG_SYS_PHYLINK_SW_RESET);
writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS);
/* reset all ports of both PHY and Link */
hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0);
hostphy_ctrl0 &= ~(HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND);
hostphy_ctrl0 |= (HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
udelay(10);
hostphy_ctrl0 &= ~(HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0);
/* HSIC phy reset */
hsic_ctrl = readl(EXYNOS5_PHY_HSIC_CTRL1);
hsic_ctrl &= ~(HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESUSPEND);
hsic_ctrl |= (HSIC_CTRL_PHYSWRST | HSIC_CTRL_UTMISWRST);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
udelay(10);
hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST | HSIC_CTRL_UTMISWRST);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);
writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);
usb_phy_control.lpa_entered = 0;
err = 1;
}
udelay(80);
return err;
}
static int exynos4_usb_phy20_init(struct platform_device *pdev)
{
u32 phypwr, phyclk, rstcon;
if (!strcmp(pdev->name, "s5p-ehci"))
set_bit(HOST_PHY_EHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s5p-ohci"))
set_bit(HOST_PHY_OHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s3c-usbgadget"))
set_bit(HOST_PHY_DEVICE, &usb_phy_control.usage);
dev_info(&pdev->dev, "usb phy usage(%ld)\n", usb_phy_control.usage);
if (exynos4_usb_phy20_is_on()) {
dev_err(&pdev->dev, "Already power on PHY\n");
return 0;
}
/*
* set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
* 0x0 : pull-up/down disabled
* 0x1 : pull-down enabled
* 0x2 : reserved
* 0x3 : pull-up enabled
*/
writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
ETC6PUD);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* USB MUX change from Device to Host */
exynos_usb_mux_change(pdev, 1);
/* set clock frequency for PLL */
phyclk = exynos_usb_phy_set_clock(pdev);
/* COMMON Block configuration during suspend */
phyclk &= ~(PHY0_COMMON_ON_N);
#ifdef CONFIG_USB_OHCI_S5P
phyclk |= PHY1_COMMON_ON_N;
#else
phyclk &= ~(PHY1_COMMON_ON_N);
#endif
writel(phyclk, EXYNOS4_PHYCLK);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* set to normal of Host */
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* reset both PHY and Link of Host */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
udelay(80);
return 0;
}
static int exynos4_check_usb_op(void)
{
u32 phypwr;
u32 op = 1;
unsigned long flags;
int ret;
ret = clk_enable(phy_clk);
if (ret)
return 0;
local_irq_save(flags);
phypwr = readl(EXYNOS4_PHYPWR);
/*If USB Device is power on, */
if (exynos_usb_device_phy_is_on()) {
op = 1;
goto done;
} else if (!exynos4_usb_host_phy_is_on()) {
op = 0;
goto done;
}
/*If USB Device & Host is suspended, */
if (soc_is_exynos4210()) {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
writel(PHY_DISABLE, S5P_USBHOST_PHY_CONTROL);
op = 0;
}
} else {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND)) {
/* unset to normal of Host */
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN
| EXYNOS4212_HSIC0_ANALOG_POWERDOWN
| EXYNOS4212_HSIC1_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
/* unset to normal of Device */
writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
op = 0;
usb_phy_control.lpa_entered = 1;
}
}
done:
local_irq_restore(flags);
clk_disable(phy_clk);
return op;
}
static int exynos4_usb_phy1_init(struct platform_device *pdev)
{
u32 phypwr;
u32 phyclk;
u32 rstcon;
if (!strcmp(pdev->name, "s5p-ehci"))
set_bit(HOST_PHY_EHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s5p-ohci"))
set_bit(HOST_PHY_OHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s3c-usbgadget"))
set_bit(HOST_PHY_DEVICE, &usb_phy_control.usage);
dev_info(&pdev->dev, "usb phy usage(%ld)\n",usb_phy_control.usage);
if (exynos4_usb_host_phy_is_on()) {
dev_err(&pdev->dev, "Already power on PHY\n");
return 0;
}
/*
* set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
* 0x0 : pull-up/down disabled
* 0x1 : pull-down enabled
* 0x2 : reserved
* 0x3 : pull-up enabled
*/
writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
ETC6PUD);
exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
/* set clock frequency for PLL */
phyclk = readl(EXYNOS4_PHYCLK) & ~(EXYNOS4210_CLKSEL_MASK);
phyclk |= exynos_usb_phy_set_clock(pdev);
#ifdef CONFIG_USB_OHCI_S5P
phyclk |= PHY1_COMMON_ON_N;
#else
phyclk &= ~(PHY1_COMMON_ON_N);
#endif
writel(phyclk, EXYNOS4_PHYCLK);
/* set to normal HSIC 0 and 1 of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* floating prevention logic: disable */
writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
udelay(80);
return 0;
}
static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
u32 rstcon;
u32 phypwr;
int err;
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* HSIC LPA: reset-resume, let cp know pda active from LPA */
/* slave wake at lpa wake ??? */
/* 12.04.27 Move start of phy1_resume, If usb cable power on the
* host phy, EHCI resume miss the PDA_ACTVIE, then CP can't send Host
* wakeup Irq */
if (!strcmp(pdev->name, "s5p-ehci"))
set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
#endif
if (exynos4_usb_host_phy_is_on()) {
/* set to resume HSIC 0 and 1 and standard of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND);
} else {
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND);
}
writel(phypwr, EXYNOS4_PHYPWR);
if (usb_phy_control.lpa_entered) {
usb_phy_control.lpa_entered = 0;
err = 1;
} else
err = 0;
} else {
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* set to normal of Host */
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
usb_phy_control.lpa_entered = 0;
err = 1;
}
udelay(80);
return err;
}
static int exynos5_usb_phy30_init(struct platform_device *pdev)
{
u32 reg;
enum usb_phy30_clk_type clk_type = DEFAULT_CLK;
exynos_usb_phy_control(USB_PHY0, PHY_ENABLE);
/* Reset USB 3.0 PHY */
writel(0x00000000, EXYNOS_USB3_PHYREG0);
writel(0x24d4e6e4, EXYNOS_USB3_PHYPARAM0);
writel(0x00000000, EXYNOS_USB3_PHYRESUME);
if (soc_is_exynos5250() && samsung_rev() < EXYNOS5250_REV_1_0) {
clk_type = EXYNOS5250_REV0_CLK;
writel(0x087fffc0, EXYNOS_USB3_LINKSYSTEM);
writel(0x03fff820, EXYNOS_USB3_PHYPARAM1);
writel(0x00000000, EXYNOS_USB3_PHYBATCHG);
/* Over-current pin is inactive on SMDK5250 rev 0.0 */
writel((readl(EXYNOS_USB3_LINKPORT) & ~(0x3<<4)) |
(0x3<<2), EXYNOS_USB3_LINKPORT);
} else {
/*
* Setting Frame Length Adjustment(FLADJ) Register.
* See xHCI 1.0 spec 5.2.4
*/
reg = EXYNOS_USB3_LINKSYSTEM_XHCI_VERSION_CONTROL |
EXYNOS_USB3_LINKSYSTEM_FLADJ(0x20);
writel(reg, EXYNOS_USB3_LINKSYSTEM);
writel(0x03fff81C, EXYNOS_USB3_PHYPARAM1);
writel(0x00000004, EXYNOS_USB3_PHYBATCHG);
#ifdef CONFIG_USB_EXYNOS_SWITCH
writel(readl(EXYNOS_USB3_LINKPORT) |
(0xf<<2), EXYNOS_USB3_LINKPORT);
#endif
/* uncomment to test 100MHz clock */
#if 0
clk_type = EXYNOS5250_REV0_CLK;
writel(readl(EXYNOS_USB3_PHYPARAM0) | (0x1<<31),
EXYNOS_USB3_PHYPARAM0);
#endif
}
/* PHYTEST POWERDOWN Control */
reg = readl(EXYNOS_USB3_PHYTEST);
reg &= ~(EXYNOS_USB3_PHYTEST_POWERDOWN_SSP |
EXYNOS_USB3_PHYTEST_POWERDOWN_HSP);
writel(reg, EXYNOS_USB3_PHYTEST);
/* UTMI Power Control */
writel(EXYNOS_USB3_PHYUTMI_OTGDISABLE, EXYNOS_USB3_PHYUTMI);
reg = exynos_usb_phy30_set_clock(pdev, clk_type);
reg |= (EXYNOS_USB3_PHYCLKRST_PORTRESET |
/* Digital power supply in normal operating mode */
EXYNOS_USB3_PHYCLKRST_RETENABLEN |
/* Enable ref clock for SS function */
EXYNOS_USB3_PHYCLKRST_REF_SSP_EN |
/* Enable spread spectrum */
EXYNOS_USB3_PHYCLKRST_SSC_EN);
if (!(soc_is_exynos5250() && samsung_rev() < EXYNOS5250_REV_1_0))
reg |= EXYNOS_USB3_PHYCLKRST_COMMONONN;
writel(reg, EXYNOS_USB3_PHYCLKRST);
udelay(10);
reg &= ~(EXYNOS_USB3_PHYCLKRST_PORTRESET);
writel(reg, EXYNOS_USB3_PHYCLKRST);
return 0;
}