static int exynos4_usb_phy0_init(struct platform_device *pdev) { u32 phypwr; u32 phyclk; u32 rstcon; exynos_usb_phy_control(USB_PHY0, PHY_ENABLE); /* set clock frequency for PLL */ phyclk = readl(EXYNOS4_PHYCLK) & ~(EXYNOS4210_CLKSEL_MASK); phyclk |= exynos_usb_phy_set_clock(pdev); phyclk &= ~(PHY0_COMMON_ON_N); writel(phyclk, EXYNOS4_PHYCLK); /* set to normal of PHY0 */ phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK; writel(phypwr, EXYNOS4_PHYPWR); /* reset all ports of both PHY and Link */ rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); udelay(10); rstcon &= ~PHY0_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); return 0; }
static int exynos4_usb_phy1_init(struct platform_device *pdev) { u32 phypwr; u32 phyclk; u32 rstcon; atomic_inc(&host_usage); if (exynos4_usb_host_phy_is_on()) { dev_err(&pdev->dev, "Already power on PHY\n"); return 0; } /* * set XuhostOVERCUR to in-active by controlling ET6PUD[15:14] * 0x0 : pull-up/down disabled * 0x1 : pull-down enabled * 0x2 : reserved * 0x3 : pull-up enabled */ writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14), ETC6PUD); exynos_usb_phy_control(USB_PHY1, PHY_ENABLE); /* set clock frequency for PLL */ phyclk = exynos_usb_phy_set_clock(pdev); phyclk &= ~(PHY1_COMMON_ON_N); writel(phyclk, EXYNOS4_PHYCLK); /* set to normal HSIC 0 and 1 of PHY1 */ phypwr = readl(EXYNOS4_PHYPWR); phypwr &= ~(PHY1_STD_NORMAL_MASK | EXYNOS4210_HSIC0_NORMAL_MASK | EXYNOS4210_HSIC1_NORMAL_MASK); writel(phypwr, EXYNOS4_PHYPWR); /* floating prevention logic: disable */ writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON); /* reset all ports of both PHY and Link */ rstcon = readl(EXYNOS4_RSTCON) | EXYNOS4210_HOST_LINK_PORT_SWRST_MASK | EXYNOS4210_PHY1_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); udelay(10); rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK | EXYNOS4210_PHY1_SWRST_MASK); writel(rstcon, EXYNOS4_RSTCON); udelay(80); return 0; }
static u32 exynos_usb_phy30_set_clock(struct platform_device *pdev, enum usb_phy30_clk_type clk_type) { u32 reg, refclk; switch (clk_type) { case EXYNOS5250_REV0_CLK: /* 100MHz diff pad clock */ reg = (EXYNOS_USB3_PHYCLKRST_REFCLKSEL(2) | EXYNOS_USB3_PHYCLKRST_FSEL(0x27) | EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x19) | EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x00)); break; case DEFAULT_CLK: default: refclk = exynos_usb_phy_set_clock(pdev); reg = EXYNOS_USB3_PHYCLKRST_REFCLKSEL(3) | EXYNOS_USB3_PHYCLKRST_FSEL(refclk); switch(refclk){ case EXYNOS5_CLKSEL_50M: reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x02) | EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x00)); break; case EXYNOS5_CLKSEL_20M: reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x7d) | EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x00)); break; case EXYNOS5_CLKSEL_19200K: reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x02) | EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x88)); break; case EXYNOS5_CLKSEL_24M: default: reg |= (EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(0x68) | EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(0x88)); break; } break; } return reg; }
static int exynos5_usb_phy20_init(struct platform_device *pdev) { u32 refclk_freq; u32 hostphy_ctrl0, otgphy_sys, hsic_ctrl, ehcictrl, ohcictrl; atomic_inc(&host_usage); if (exynos5_usb_host_phy20_is_on()) { dev_err(&pdev->dev, "Already power on PHY\n"); return 0; } exynos_usb_mux_change(pdev, 1); exynos_usb_phy_control(USB_PHY1, PHY_ENABLE); /* Host and Device should be set at the same time */ hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0); hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK); otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS); otgphy_sys &= ~(OTG_SYS_CTRL0_FSEL_MASK); /* 2.0 phy reference clock configuration */ refclk_freq = exynos_usb_phy_set_clock(pdev); hostphy_ctrl0 |= (refclk_freq << HOST_CTRL0_CLKSEL_SHIFT); otgphy_sys |= (refclk_freq << OTG_SYS_CLKSEL_SHIFT); /* COMMON Block configuration during suspend */ hostphy_ctrl0 |= HOST_CTRL0_COMMONON_N; otgphy_sys &= ~(OTG_SYS_COMMON_ON); /* otg phy reset */ otgphy_sys &= ~(OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG | OTG_SYS_FORCE_SLEEP); otgphy_sys &= ~(OTG_SYS_REF_CLK_SEL_MASK); otgphy_sys |= (OTG_SYS_REF_CLK_SEL(0x2) | OTG_SYS_OTGDISABLE); otgphy_sys |= (OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG | OTG_SYS_PHYLINK_SW_RESET); writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS); udelay(10); otgphy_sys &= ~(OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG | OTG_SYS_PHYLINK_SW_RESET); writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS); /* host phy reset */ hostphy_ctrl0 &= ~(HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL | HOST_CTRL0_SIDDQ); hostphy_ctrl0 &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); hostphy_ctrl0 |= (HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0); udelay(10); hostphy_ctrl0 &= ~(HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0); /* HSIC phy reset */ hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) | HSIC_CTRL_PHYSWRST); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); udelay(10); hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); udelay(80); /* enable EHCI DMA burst */ ehcictrl = readl(EXYNOS5_PHY_HOST_EHCICTRL); ehcictrl |= (EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4 | EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16); writel(ehcictrl, EXYNOS5_PHY_HOST_EHCICTRL); /* set ohci_suspend_on_n */ ohcictrl = readl(EXYNOS5_PHY_HOST_OHCICTRL); ohcictrl |= OHCICTRL_SUSPLGCY; writel(ohcictrl, EXYNOS5_PHY_HOST_OHCICTRL); return 0; }
static int exynos4_usb_phy20_init(struct platform_device *pdev) { u32 phypwr, phyclk, rstcon; if (!strcmp(pdev->name, "s5p-ehci")) set_bit(HOST_PHY_EHCI, &usb_phy_control.usage); else if (!strcmp(pdev->name, "s5p-ohci")) set_bit(HOST_PHY_OHCI, &usb_phy_control.usage); else if (!strcmp(pdev->name, "s3c-usbgadget")) set_bit(HOST_PHY_DEVICE, &usb_phy_control.usage); dev_info(&pdev->dev, "usb phy usage(%ld)\n", usb_phy_control.usage); if (exynos4_usb_phy20_is_on()) { dev_err(&pdev->dev, "Already power on PHY\n"); return 0; } /* * set XuhostOVERCUR to in-active by controlling ET6PUD[15:14] * 0x0 : pull-up/down disabled * 0x1 : pull-down enabled * 0x2 : reserved * 0x3 : pull-up enabled */ writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14), ETC6PUD); exynos_usb_phy_control(USB_PHY | USB_PHY_HSIC0 | USB_PHY_HSIC1, PHY_ENABLE); /* USB MUX change from Device to Host */ exynos_usb_mux_change(pdev, 1); /* set clock frequency for PLL */ phyclk = exynos_usb_phy_set_clock(pdev); /* COMMON Block configuration during suspend */ phyclk &= ~(PHY0_COMMON_ON_N); #ifdef CONFIG_USB_OHCI_S5P phyclk |= PHY1_COMMON_ON_N; #else phyclk &= ~(PHY1_COMMON_ON_N); #endif writel(phyclk, EXYNOS4_PHYCLK); /* set to normal of Device */ phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK; writel(phypwr, EXYNOS4_PHYPWR); /* set to normal of Host */ phypwr = readl(EXYNOS4_PHYPWR); phypwr &= ~(PHY1_STD_NORMAL_MASK | EXYNOS4212_HSIC0_NORMAL_MASK | EXYNOS4212_HSIC1_NORMAL_MASK); writel(phypwr, EXYNOS4_PHYPWR); /* reset both PHY and Link of Device */ rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); udelay(10); rstcon &= ~PHY0_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); /* reset both PHY and Link of Host */ rstcon = readl(EXYNOS4_RSTCON) | EXYNOS4212_HOST_LINK_PORT_SWRST_MASK | EXYNOS4212_PHY1_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); udelay(10); rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK | EXYNOS4212_PHY1_SWRST_MASK); writel(rstcon, EXYNOS4_RSTCON); udelay(80); return 0; }
static int exynos4_usb_phy1_init(struct platform_device *pdev) { u32 phypwr; u32 phyclk; u32 rstcon; if (!strcmp(pdev->name, "s5p-ehci")) set_bit(HOST_PHY_EHCI, &usb_phy_control.usage); else if (!strcmp(pdev->name, "s5p-ohci")) set_bit(HOST_PHY_OHCI, &usb_phy_control.usage); else if (!strcmp(pdev->name, "s3c-usbgadget")) set_bit(HOST_PHY_DEVICE, &usb_phy_control.usage); dev_info(&pdev->dev, "usb phy usage(%ld)\n",usb_phy_control.usage); if (exynos4_usb_host_phy_is_on()) { dev_err(&pdev->dev, "Already power on PHY\n"); return 0; } /* * set XuhostOVERCUR to in-active by controlling ET6PUD[15:14] * 0x0 : pull-up/down disabled * 0x1 : pull-down enabled * 0x2 : reserved * 0x3 : pull-up enabled */ writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14), ETC6PUD); exynos_usb_phy_control(USB_PHY1, PHY_ENABLE); /* set clock frequency for PLL */ phyclk = readl(EXYNOS4_PHYCLK) & ~(EXYNOS4210_CLKSEL_MASK); phyclk |= exynos_usb_phy_set_clock(pdev); #ifdef CONFIG_USB_OHCI_S5P phyclk |= PHY1_COMMON_ON_N; #else phyclk &= ~(PHY1_COMMON_ON_N); #endif writel(phyclk, EXYNOS4_PHYCLK); /* set to normal HSIC 0 and 1 of PHY1 */ phypwr = readl(EXYNOS4_PHYPWR); phypwr &= ~(PHY1_STD_NORMAL_MASK | EXYNOS4210_HSIC0_NORMAL_MASK | EXYNOS4210_HSIC1_NORMAL_MASK); writel(phypwr, EXYNOS4_PHYPWR); /* floating prevention logic: disable */ writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON); /* reset all ports of both PHY and Link */ rstcon = readl(EXYNOS4_RSTCON) | EXYNOS4210_HOST_LINK_PORT_SWRST_MASK | EXYNOS4210_PHY1_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); udelay(10); rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK | EXYNOS4210_PHY1_SWRST_MASK); writel(rstcon, EXYNOS4_RSTCON); udelay(80); return 0; }
static int exynos4_usb_phy20_init(struct platform_device *pdev) { u32 phypwr, phyclk, rstcon; //printk("[exynos4_usb_phy20_init]++++++++++++++\n"); atomic_inc(&host_usage); if (exynos4_usb_phy20_is_on()) { //dev_err(&pdev->dev, "Already power on PHY\n"); /*diog.zhao,0614,remove*/ //if(USB_PHY_L2 == usb_phy_control.status) //return -1; return 0; } if(USB_PHY_L0 == usb_phy_control.status) return 0; /* * set XuhostOVERCUR to in-active by controlling ET6PUD[15:14] * 0x0 : pull-up/down disabled * 0x1 : pull-down enabled * 0x2 : reserved * 0x3 : pull-up enabled */ writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14), ETC6PUD); exynos_usb_phy_control(USB_PHY | USB_PHY_HSIC0 | USB_PHY_HSIC1, PHY_ENABLE); /* USB MUX change from Device to Host */ exynos_usb_mux_change(pdev, 1); /* set clock frequency for PLL */ phyclk = exynos_usb_phy_set_clock(pdev); /* COMMON Block configuration during suspend */ phyclk &= ~(PHY0_COMMON_ON_N | PHY1_COMMON_ON_N); writel(phyclk, EXYNOS4_PHYCLK); /* set to normal of Device */ phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK; writel(phypwr, EXYNOS4_PHYPWR); /* set to normal of Host */ phypwr = readl(EXYNOS4_PHYPWR); phypwr &= ~(PHY1_STD_NORMAL_MASK | EXYNOS4212_HSIC0_NORMAL_MASK | EXYNOS4212_HSIC1_NORMAL_MASK); writel(phypwr, EXYNOS4_PHYPWR); /* reset both PHY and Link of Device */ rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); udelay(10); rstcon &= ~PHY0_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); /* reset both PHY and Link of Host */ rstcon = readl(EXYNOS4_RSTCON) | EXYNOS4212_HOST_LINK_PORT_SWRST_MASK | EXYNOS4212_PHY1_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); udelay(10); rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK | EXYNOS4212_PHY1_SWRST_MASK); writel(rstcon, EXYNOS4_RSTCON); udelay(80); usb_phy_control.status = USB_PHY_L0; return 0; }