static sw_error_t _athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_speed_t * pspeed) { sw_error_t rv; a_uint32_t phy_id; HSL_DEV_ID_CHECK(dev_id); if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) { return SW_BAD_PARAM; } rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); SW_RTN_ON_ERROR(rv); rv = f2_phy_get_speed(dev_id, phy_id, pspeed); return rv; }
/****************************************************************************** * * f2_phy_set_duplex - Determines the speed of phy ports associated with the * specified device. * * RETURNS: * AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX; * AG7100_PHY_SPEED_1000T; */ sw_error_t f2_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_duplex_t duplex) { a_uint16_t phy_data = 0; a_uint16_t phy_status = 0; fal_port_speed_t old_speed; a_uint32_t autoneg, oldneg; if (f2_phy_autoneg_status(dev_id, phy_id)) phy_data &= ~F2_CTRL_AUTONEGOTIATION_ENABLE; (void)f2_phy_get_autoneg_adv(dev_id, phy_id, &autoneg); oldneg = autoneg; autoneg &= ~FAL_PHY_ADV_FE_SPEED_ALL; (void)f2_phy_get_speed(dev_id, phy_id, &old_speed); if (old_speed == FAL_SPEED_100) phy_data |= F2_CTRL_SPEED_100; else if (old_speed == FAL_SPEED_10) phy_data |= F2_CTRL_SPEED_10; else return SW_FAIL; if (duplex == FAL_FULL_DUPLEX) { phy_data |= F2_CTRL_FULL_DUPLEX; if (old_speed == FAL_SPEED_100) autoneg = FAL_PHY_ADV_100TX_FD; else autoneg = FAL_PHY_ADV_10T_FD; } else if (duplex == FAL_HALF_DUPLEX) { phy_data &= ~F2_CTRL_FULL_DUPLEX; if (old_speed == FAL_SPEED_100) autoneg = FAL_PHY_ADV_100TX_HD; else autoneg = FAL_PHY_ADV_10T_HD; } else return SW_BAD_PARAM; (void)f2_phy_set_autoneg_adv(dev_id, phy_id, autoneg); (void)f2_phy_restart_autoneg(dev_id, phy_id); if(f2_phy_get_link_status(dev_id, phy_id)) { do { phy_status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS); } while(!F2_AUTONEG_DONE(phy_status)); } f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, phy_data); (void)f2_phy_set_autoneg_adv(dev_id, phy_id, oldneg); return SW_OK; }