/* * Given the following ... * * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' * compatible string and 'addr' physical address) * * 2) An Fman port * * ... update the phy-handle property of the Ethernet node to point to the * right PHY. This assumes that we already know the PHY for each port. * * The offset of the Fman Ethernet node is also passed in for convenience, but * it is not used, and we recalculate the offset anyway. * * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. * Inside the Fman, "ports" are things that connect to MACs. We only call them * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs * and ports are the same thing. * */ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { phy_interface_t intf = fm_info_get_enet_if(port); char phy[16]; /* The RGMII PHY is identified by the MAC connected to it */ if (intf == PHY_INTERFACE_MODE_RGMII) { sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2); fdt_set_phy_handle(fdt, compat, addr, phy); } /* The SGMII PHY is identified by the MAC connected to it */ if (intf == PHY_INTERFACE_MODE_SGMII) { int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + port); u8 slot; if (lane < 0) return; slot = lane_to_slot[lane]; if (slot) { /* Slot housing a SGMII riser card */ sprintf(phy, "phy_s%x_%02x", slot, (fm_info_get_phy_address(port - FM1_DTSEC1)- CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1)); fdt_set_phy_handle(fdt, compat, addr, phy); } } }
/* * Given the following ... * * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' * compatible string and 'addr' physical address) * * 2) An Fman port * * ... update the phy-handle property of the Ethernet node to point to the * right PHY. This assumes that we already know the PHY for each port. That * information is stored in mdio_mux[]. * * The offset of the Fman Ethernet node is also passed in for convenience, but * it is not used, and we recalculate the offset anyway. * * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. * Inside the Fman, "ports" are things that connect to MACs. We only call them * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs * and ports are the same thing. * * Note that this code would be cleaner if had a function called * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[] * array. That's because all we're doing is figuring out the PHY address for * a given Fman MAC and writing it to the device tree. Well, we already did * the hard work to figure that out in board_eth_init(), so it's silly to * repeat that here. */ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask; char phy[16]; if (port == FM1_10GEC1) { /* XAUI */ int lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { /* The XAUI PHY is identified by the slot */ sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); fdt_set_phy_handle(fdt, compat, addr, phy); } return; } if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) { /* RGMII */ /* The RGMII PHY is identified by the MAC connected to it */ sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); fdt_set_phy_handle(fdt, compat, addr, phy); return; } /* If it's not RGMII or XGMII, it must be SGMII */ if (mux) { /* The SGMII PHY is identified by the MAC connected to it */ sprintf(phy, "phy_sgmii_%x", CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } }
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { struct fixed_link f_link; if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) { if (port == FM1_DTSEC3) { fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2"); fdt_setprop_string(fdt, offset, "phy-connection-type", "rgmii"); fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { if (port == FM1_DTSEC1) { fdt_set_phy_handle(fdt, compat, addr, "sgmii_vsc8234_phy_s5"); } else if (port == FM1_DTSEC2) { fdt_set_phy_handle(fdt, compat, addr, "sgmii_vsc8234_phy_s4"); } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { if (port == FM1_DTSEC3) { fdt_set_phy_handle(fdt, compat, addr, "sgmii_aqr105_phy_s3"); } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2"); break; case FM1_DTSEC3: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3"); break; case FM1_DTSEC4: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4"); break; default: break; } fdt_delprop(fdt, offset, "phy-connection-type"); fdt_setprop_string(fdt, offset, "phy-connection-type", "qsgmii"); fdt_status_okay_by_alias(fdt, "emi1_slot2"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { /* XFI interface */ f_link.phy_id = port; f_link.duplex = 1; f_link.link_speed = 10000; f_link.pause = 0; f_link.asym_pause = 0; /* no PHY for XFI */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); } }
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) { if (mdio_mux[port] == EMI1_RGMII) fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); if (mdio_mux[port] == EMI1_SLOT3) { int idx = port - FM2_DTSEC1 + 5; char phy[16]; sprintf(phy, "phy%d_slot3", idx); fdt_set_phy_handle(blob, prop, pa, phy); } }
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) { if (mdio_mux[port] == EMI1_RGMII) fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); /* TODO: will do with dts */ }
/* * Given the following ... * * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' * compatible string and 'addr' physical address) * * 2) An Fman port * * ... update the phy-handle property of the Ethernet node to point to the * right PHY. This assumes that we already know the PHY for each port. * * The offset of the Fman Ethernet node is also passed in for convenience, but * it is not used, and we recalculate the offset anyway. * * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. * Inside the Fman, "ports" are things that connect to MACs. We only call them * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs * and ports are the same thing. * */ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { phy_interface_t intf = fm_info_get_enet_if(port); char phy[16]; /* The RGMII PHY is identified by the MAC connected to it */ if (intf == PHY_INTERFACE_MODE_RGMII) { sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); fdt_set_phy_handle(fdt, compat, addr, phy); } /* The SGMII PHY is identified by the MAC connected to it */ if (intf == PHY_INTERFACE_MODE_SGMII) { int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); u8 slot; if (lane < 0) return; slot = lane_to_slot[lane]; if (slot) { sprintf(phy, "phy_sgmii_%x", CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } else { sprintf(phy, "phy_sgmii_%x", CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } } if (intf == PHY_INTERFACE_MODE_XGMII) { /* XAUI */ int lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { /* The XAUI PHY is identified by the slot */ sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); fdt_set_phy_handle(fdt, compat, addr, phy); } } }
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { #if defined(CONFIG_T1024RDB) if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) || (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && (port == FM1_DTSEC3)) { fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); fdt_setprop_string(fdt, offset, "phy-connection-type", "sgmii-2500"); fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); } #endif }
/* * Given the following ... * * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' * compatible string and 'addr' physical address) * * 2) An Fman port * * ... update the phy-handle property of the Ethernet node to point to the * right PHY. This assumes that we already know the PHY for each port. That * information is stored in mdio_mux[]. * * The offset of the Fman Ethernet node is also passed in for convenience, but * it is not used. * * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. * Inside the Fman, "ports" are things that connect to MACs. We only call them * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs * and ports are the same thing. */ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { enum srds_prtcl device; int lane, slot, phy; char alias[32]; /* RGMII and XGMII are already mapped correctly in the DTS */ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { device = serdes_device_from_fm_port(port); lane = serdes_get_first_lane(device); slot = lane_to_slot[lane]; phy = fm_info_get_phy_address(port); sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); fdt_set_phy_handle(fdt, compat, addr, alias); } }
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { int phy; char alias[32]; struct fixed_link f_link; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { phy = fm_info_get_phy_address(port); sprintf(alias, "phy_sgmii_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, alias); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { /* check if it's XFI interface for 10g */ switch (prtcl2) { case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0xb1: case 0xb2: f_link.phy_id = port; f_link.duplex = 1; f_link.link_speed = 10000; f_link.pause = 0; f_link.asym_pause = 0; fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); break; case 0x98: /* XAUI interface */ strcpy(alias, "phy_xaui_slot1"); fdt_status_okay_by_alias(fdt, alias); strcpy(alias, "phy_xaui_slot2"); fdt_status_okay_by_alias(fdt, alias); break; case 0x9e: /* XAUI interface */ case 0x9a: case 0x93: case 0x91: strcpy(alias, "phy_xaui_slot1"); fdt_status_okay_by_alias(fdt, alias); break; case 0x97: /* XAUI interface */ case 0xc3: strcpy(alias, "phy_xaui_slot2"); fdt_status_okay_by_alias(fdt, alias); break; default: break; } } }
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { struct fixed_link f_link; if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { if (port == FM1_DTSEC9) { fdt_set_phy_handle(fdt, compat, addr, "sgmii_riser_s1_p1"); } else if (port == FM1_DTSEC2) { fdt_set_phy_handle(fdt, compat, addr, "sgmii_riser_s2_p1"); } else if (port == FM1_DTSEC5) { fdt_set_phy_handle(fdt, compat, addr, "sgmii_riser_s3_p1"); } else if (port == FM1_DTSEC6) { fdt_set_phy_handle(fdt, compat, addr, "sgmii_riser_s4_p1"); } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { /* 2.5G SGMII interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); f_link.link_speed = cpu_to_fdt32(1000); f_link.pause = 0; f_link.asym_pause = 0; /* no PHY for 2.5G SGMII */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", "sgmii-2500"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (mdio_mux[port]) { case EMI1_SLOT1: switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s1_p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s1_p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s1_p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s1_p4"); break; default: break; } break; case EMI1_SLOT2: switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4"); break; default: break; } break; default: break; } fdt_delprop(fdt, offset, "phy-connection-type"); fdt_setprop_string(fdt, offset, "phy-connection-type", "qsgmii"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && port == FM1_10GEC1) { /* XFI interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); f_link.link_speed = cpu_to_fdt32(10000); f_link.pause = 0; f_link.asym_pause = 0; /* no PHY for XFI */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); } }
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { struct fixed_link f_link; const u32 *handle; const char *prop = NULL; int off; if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { switch (port) { case FM1_DTSEC9: fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1"); break; case FM1_DTSEC10: fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1"); break; default: break; } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { /* 2.5G SGMII interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); f_link.link_speed = cpu_to_fdt32(1000); f_link.pause = 0; f_link.asym_pause = 0; /* no PHY for 2.5G SGMII on QDS */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", "sgmii-2500"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1"); break; case FM1_DTSEC10: fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3"); break; default: break; } fdt_delprop(fdt, offset, "phy-connection-type"); fdt_setprop_string(fdt, offset, "phy-connection-type", "qsgmii"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && (port == FM1_10GEC1 || port == FM1_10GEC2)) { handle = fdt_getprop(fdt, offset, "phy-handle", NULL); prop = NULL; if (handle) { off = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*handle)); prop = fdt_getprop(fdt, off, "backplane-mode", NULL); } if (!prop || strcmp(prop, "10gbase-kr")) { /* XFI interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); f_link.link_speed = cpu_to_fdt32(10000); f_link.pause = 0; f_link.asym_pause = 0; /* no PHY for XFI */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); } } }
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { int phy; char alias[20]; char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; char buf[32] = "serdes-1,"; struct fixed_link f_link; int media_type = 0; int off; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_T2080QDS serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); #endif u32 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { phy = fm_info_get_phy_address(port); switch (port) { #if defined(CONFIG_T2080QDS) case FM1_DTSEC1: if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { media_type = 1; fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx1"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); sprintf(buf, "%s%s%s", buf, "lane-c,", (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIH_KX_MASK); break; } case FM1_DTSEC2: if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { media_type = 1; fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx2"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); sprintf(buf, "%s%s%s", buf, "lane-d,", (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIG_KX_MASK); break; } case FM1_DTSEC9: if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { media_type = 1; fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx9"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); sprintf(buf, "%s%s%s", buf, "lane-a,", (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIE_KX_MASK); break; } case FM1_DTSEC10: if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { media_type = 1; fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx10"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio10"); sprintf(buf, "%s%s%s", buf, "lane-b,", (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIF_KX_MASK); break; } if (mdio_mux[port] == EMI1_SLOT2) { sprintf(alias, "phy_sgmii_s2_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot2"); } else if (mdio_mux[port] == EMI1_SLOT3) { sprintf(alias, "phy_sgmii_s3_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot3"); } break; case FM1_DTSEC5: if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { media_type = 1; fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx5"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); sprintf(buf, "%s%s%s", buf, "lane-g,", (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIC_KX_MASK); break; } case FM1_DTSEC6: if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { media_type = 1; fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx6"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); sprintf(buf, "%s%s%s", buf, "lane-h,", (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIID_KX_MASK); break; } if (mdio_mux[port] == EMI1_SLOT1) { sprintf(alias, "phy_sgmii_s1_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot1"); } else if (mdio_mux[port] == EMI1_SLOT2) { sprintf(alias, "phy_sgmii_s2_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot2"); } break; #elif defined(CONFIG_T2081QDS) case FM1_DTSEC1: case FM1_DTSEC2: case FM1_DTSEC5: case FM1_DTSEC6: case FM1_DTSEC9: case FM1_DTSEC10: if (mdio_mux[port] == EMI1_SLOT2) { sprintf(alias, "phy_sgmii_s2_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot2"); } else if (mdio_mux[port] == EMI1_SLOT3) { sprintf(alias, "phy_sgmii_s3_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot3"); } else if (mdio_mux[port] == EMI1_SLOT5) { sprintf(alias, "phy_sgmii_s5_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot5"); } else if (mdio_mux[port] == EMI1_SLOT6) { sprintf(alias, "phy_sgmii_s6_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot6"); } else if (mdio_mux[port] == EMI1_SLOT7) { sprintf(alias, "phy_sgmii_s7_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot7"); } break; #endif default: break; } if (media_type) { /* set property for 1000BASE-KX in dtb */ off = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", addr + 0x1000); fdt_setprop_string(fdt, off, "lane-instance", buf); } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { switch (srds_s1) { case 0x66: /* XFI interface */ case 0x6b: case 0x6c: case 0x6d: case 0x71: /* * if the 10G is XFI, check hwconfig to see what is the * media type, there are two types, fiber or copper, * fix the dtb accordingly. */ switch (port) { case FM1_10GEC1: if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { /* it's MAC9 */ media_type = 1; fdt_set_phy_handle(fdt, compat, addr, "phy_xfi9"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); sprintf(buf, "%s%s%s", buf, "lane-a,", (char *)lane_mode[1]); } break; case FM1_10GEC2: if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { /* it's MAC10 */ media_type = 1; fdt_set_phy_handle(fdt, compat, addr, "phy_xfi10"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); sprintf(buf, "%s%s%s", buf, "lane-b,", (char *)lane_mode[1]); } break; case FM1_10GEC3: if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { /* it's MAC1 */ media_type = 1; fdt_set_phy_handle(fdt, compat, addr, "phy_xfi1"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); sprintf(buf, "%s%s%s", buf, "lane-c,", (char *)lane_mode[1]); } break; case FM1_10GEC4: if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { /* it's MAC2 */ media_type = 1; fdt_set_phy_handle(fdt, compat, addr, "phy_xfi2"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); sprintf(buf, "%s%s%s", buf, "lane-d,", (char *)lane_mode[1]); } break; default: return; } if (!media_type) { /* fixed-link is used for XFI fiber cable */ f_link.phy_id = port; f_link.duplex = 1; f_link.link_speed = 10000; f_link.pause = 0; f_link.asym_pause = 0; fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); } else { /* set property for copper cable */ off = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", addr + 0x1000); fdt_setprop_string(fdt, off, "lane-instance", buf); } break; default: break; } } }
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) { int interface = fm_info_get_enet_if(port); if (interface == PHY_INTERFACE_MODE_SGMII || interface == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy21"); break; case FM1_DTSEC2: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy22"); break; case FM1_DTSEC3: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy23"); break; case FM1_DTSEC4: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy24"); break; case FM1_DTSEC6: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy12"); break; case FM1_DTSEC9: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy14"); else fdt_set_phy_handle(blob, prop, pa, "phy_sgmii4"); break; case FM1_DTSEC10: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy13"); else fdt_set_phy_handle(blob, prop, pa, "phy_sgmii3"); break; case FM2_DTSEC1: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy41"); break; case FM2_DTSEC2: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy42"); break; case FM2_DTSEC3: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy43"); break; case FM2_DTSEC4: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy44"); break; case FM2_DTSEC6: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy32"); break; case FM2_DTSEC9: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy34"); else fdt_set_phy_handle(blob, prop, pa, "phy_sgmii12"); break; case FM2_DTSEC10: if (qsgmiiphy_fix[port]) fdt_set_phy_handle(blob, prop, pa, "sgmii_phy33"); else fdt_set_phy_handle(blob, prop, pa, "phy_sgmii11"); break; default: break; } } }
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { int phy; char alias[20]; struct fixed_link f_link; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { phy = fm_info_get_phy_address(port); switch (port) { case FM1_DTSEC1: case FM1_DTSEC2: case FM1_DTSEC9: case FM1_DTSEC10: sprintf(alias, "phy_sgmii_s3_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot3"); break; case FM1_DTSEC5: case FM1_DTSEC6: if (mdio_mux[port] == EMI1_SLOT1) { sprintf(alias, "phy_sgmii_s1_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot1"); } else if (mdio_mux[port] == EMI1_SLOT2) { sprintf(alias, "phy_sgmii_s2_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); fdt_status_okay_by_alias(fdt, "emi1_slot2"); } break; default: break; } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { switch (srds_s1) { case 0x66: /* XFI interface */ case 0x6b: case 0x6c: case 0x6d: case 0x71: f_link.phy_id = port; f_link.duplex = 1; f_link.link_speed = 10000; f_link.pause = 0; f_link.asym_pause = 0; /* no PHY for XFI */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); break; default: break; } } }