static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buffer)
{
unsigned device;
struct resource *res;
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_block_write(res->base, device, cmd, bytes, buffer);
}
static void hudson_lpc_set_resources(struct device *dev)
{
struct resource *res;
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
res = find_resource(dev, 2);
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
pci_dev_set_resources(dev);
}
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
{
unsigned device;
struct resource *res;
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_write_byte(res->base, device, address, val);
}
static int lsmbus_recv_byte(device_t dev)
{
unsigned device;
struct resource *res;
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
return do_smbus_recv_byte(res->base, device);
}
void
free_resource(fc_resource_t **head, void *ptr, int (cmp)(void *, void *))
{
fc_resource_t *r;
if ((r = find_resource(head, ptr, cmp)) != NULL)
r->data = NULL;
else
log_message(MSG_ERROR, "free_resource: No such Entry: %p\n",
ptr);
}
static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
return do_smbus_write_byte(res->base, device, address, data);
}
static void mcp55_sm_init(device_t dev)
{
#if CONFIG_GENERATE_ACPI_TABLES == 1
struct resource *res;
res = find_resource(dev, 0x60);
if (res)
pm_base = res->base;
#endif
}
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t data)
{
uint16_t device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_write_byte(res->base, device, address, data);
}
void lpc_set_resources(struct device *dev)
{
struct resource *res;
pci_dev_set_resources(dev);
/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
res = find_resource(dev, SPIROM_BASE_ADDRESS);
pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
}
static void sb800_lpc_set_resources(struct device *dev)
{
struct resource *res;
pci_dev_set_resources(dev);
/* Special case. SPI Base Address. The SpiRomEnable should be set. */
res = find_resource(dev, 0xA0);
pci_write_config32(dev, 0xA0, res->base | 1 << 1);
}
static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return smbus_write8(res->base, device, address, data);
}
static int lsmbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buf)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
return do_smbus_block_read(res->base, device, cmd, bytes, buf);
}
void load_rumoured_servers()
{
struct string_t *filename = new_string_string(emergence_home_dir);
#ifdef EMCLIENT
string_cat_text(filename, "/rumoured.client");
struct stat buf;
if(stat(filename->text, &buf) == -1)
{
free_string(filename);
filename = new_string_text(find_resource("rumoured.client"));
}
#endif
#ifdef EMSERVER
string_cat_text(filename, "/rumoured.server.");
string_cat_int(filename, net_listen_port);
#endif
FILE *file = fopen(filename->text, "r");
free_string(filename);
if(!file)
return;
// flockfile(file);
char *name = NULL;
uint16_t port;
struct server_t server;
while(fscanf(file, "%a[^:]:%hu %u\n", &name, &port, (uint32_t*)&server.time) == 3)
{
int r = inet_pton(AF_INET, name, &server.ip);
free(name);
name = NULL;
if(r <= 0)
continue;
server.port = htons(port);
LL_ADD_TAIL(struct server_t, &rumoured_servers, &server);
}
if(name)
{
free(name);
name = NULL;
}
fclose(file);
}
int resman_add(struct resman *rman, const char *fname, void *data)
{
int ridx;
if((ridx = find_resource(rman, fname)) != -1) {
return ridx;
}
/* resource not found, create a new one and start a loading job */
return add_resource(rman, fname, data);
}
unsigned long acpi_fill_madt(unsigned long current)
{
unsigned int irq_start = 0;
device_t dev = 0;
struct resource* res = NULL;
// SJM: Hard-code CPU LAPIC entries for now
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7);
// Southbridge IOAPIC
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start);
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
// P64H2 Bus B IOAPIC
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
if (!dev)
BUG(); // Config.lb error?
res = find_resource(dev, PCI_BASE_ADDRESS_0);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start);
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
// P64H2 Bus A IOAPIC
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
if (!dev)
BUG(); // Config.lb error?
res = find_resource(dev, PCI_BASE_ADDRESS_0);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start);
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
// Map ISA IRQ 0 to IRQ 2
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
// IRQ9 differs from ISA standard - ours is active high, level-triggered
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
return current;
}
void lpc_set_resources(struct device *dev)
{
struct resource *res;
printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n");
pci_dev_set_resources(dev);
/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
res = find_resource(dev, SPIROM_BASE_ADDRESS);
pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n");
}
static u32 get_sm_mmio(struct device *dev)
{
struct resource *res;
struct bus *pbus;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x90);
if (res->base == SMB_BASE_ADDR)
return SMBUS_MMIO_BASE;
return ASF_MMIO_BASE;
}
static void sb600_sm_set_resources(struct device *dev)
{
struct resource *res;
u8 byte;
pci_dev_set_resources(dev);
/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */
byte = pm_ioread(0x52);
byte |= 1 << 6;
pm_iowrite(0x52, byte);
res = find_resource(dev, 0x74);
pci_write_config32(dev, 0x74, res->base | 1 << 3);
res = find_resource(dev, 0x14);
pci_write_config32(dev, 0x14, res->base);
res = find_resource(dev, 0x10);
pci_write_config32(dev, 0x10, res->base | 1);
}
static int lsmbus_read_byte(device_t dev, u8 address)
{
u16 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_read_byte(res->base, device, address);
}
static void hudson_lpc_set_resources(struct device *dev)
{
struct resource *res;
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER);
res->base |= PCI_COMMAND_MEMORY;
pci_dev_set_resources(dev);
}
static void sb700_sm_set_resources(struct device *dev)
{
struct resource *res;
u8 byte;
pci_dev_set_resources(dev);
res = find_resource(dev, 0x74);
pci_write_config32(dev, 0x74, res->base | 1 << 3);
/* TODO: test hpet */
#if 0 //rrg-2.0.3 shows BAR1 not used
/* Make SMBUS BAR1(HPET base at offset 14h) visible */
byte = pci_read_config8(dev, 0x43);
byte &= ~(1 << 3);
pci_write_config8(dev, 0x43, byte);
#endif
res = find_resource(dev, 0xB4);
/* Program HPET BAR Address */
pci_write_config32(dev, 0xB4, res->base);
/* Enable decoding of HPET MMIO, enable HPET MSI */
byte = pci_read_config8(dev, 0x43);
//byte |= (1 << 3); // Make SMBus Bar1 invisible
//byte |= ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
byte |= (1 << 4);
pci_write_config8(dev, 0x43, byte);
/* Enable HPET irq */
byte = pci_read_config8(dev, 0x65);
byte |= (1 << 2);
pci_write_config8(dev, 0x65, byte);
/* TODO: End of test hpet */
res = find_resource(dev, PRIMARY_SMBUS_RESOURCE_NUMBER);
pci_write_config32(dev, PRIMARY_SMBUS_RESOURCE_NUMBER, res->base | 1);
res = find_resource(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER);
pci_write_config32(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER, res->base | 1);
}
static void azalia_init(struct device *dev)
{
#if IS_ENABLED(CONFIG_MCP55_USE_AZA)
u8 *base;
u32 codec_mask, reg32;
struct resource *res;
u8 reg8;
/* Set bus master. */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // TODO: Unused?
reg8 = pci_read_config8(dev, 0x40);
reg8 |= (1 << 3); /* Clear Clock Detect bit. */
pci_write_config8(dev, 0x40, reg8);
reg8 &= ~(1 << 3); /* Keep CLKDETCLR from clearing the bit over and over. */
pci_write_config8(dev, 0x40, reg8);
reg8 |= (1 << 2); /* Enable clock detection. */
pci_write_config8(dev, 0x40, reg8);
mdelay(1);
reg8 = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "Azalia: codec type: %s\n",
(reg8 & (1 << 1)) ? "Azalia" : "AC97");
reg8 = pci_read_config8(dev, 0x40); /* Audio control */
reg8 |= 1; /* Select Azalia mode. TODO: Control via devicetree.cb. */
pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); /* Docking status. */
reg8 &= ~(1 << 7); /* Docking not supported. */
pci_write_config8(dev, 0x4d, reg8);
res = find_resource(dev, 0x10);
if (!res)
return;
/*
* NOTE: This will break as soon as the Azalia gets a BAR above
* 4G. Is there anything we can do about it?
*/
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
codecs_init(dev, base, codec_mask);
}
#endif
}
static void usb2_init(struct device *dev)
{
u32 base;
struct resource *res;
print_debug("USB 2.0 INIT:---------->\n");
//-------------- enable USB2.0 (SiS7002) -------------------------
{
u8 temp8;
int i=0;
while(SiS_SiS7002_init[i][0] != 0)
{
temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
temp8 &= SiS_SiS7002_init[i][1];
temp8 |= SiS_SiS7002_init[i][2];
pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
i++;
};
}
res = find_resource(dev, 0x10);
if(!res)
return;
base = res->base;
printk(BIOS_DEBUG, "base = 0x%08x\n", base);
write32(base+0x20, 0x2);
//-----------------------------------------------------------
#if DEBUG_USB2
{
int i;
print_debug("****** USB 2.0 PCI config ******");
print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
if((i%16)==0){
print_debug("\n");
print_debug_hex8(i);
print_debug(": ");
}
print_debug_hex32(pci_read_config32(dev,i));
print_debug(" ");
}
print_debug("\n");
}
#endif
print_debug("USB 2.0 INIT:<----------\n");
}
int allocate_resource(Resource_s * psRoot, Resource_s * psNew,
uint nSize, uint nMin, uint nMax, uint nAlign,
void (* pfnAlign)(void * pData, Resource_s * psRes, uint nSize, uint nAlign),
void * pAlignData)
{
int nErr;
RWL_LOCK_RW(g_hResourceLock);
nErr = find_resource(psRoot, psNew, nSize, nMin, nMax, nAlign, pfnAlign, pAlignData);
if(nErr>=0 && __request_resource(psRoot, psNew))
nErr = -EBUSY;
RWL_UNLOCK_RW(g_hResourceLock);
return nErr;
}
static void pch_smbus_init(struct device *dev)
{
struct resource *res;
/* Enable clock gating */
pci_update_config32(dev, 0x80,
~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)), 0);
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
}
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
{
unsigned device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4));
return do_smbus_write_byte(res->base, device, address, val);
}
static int lsmbus_recv_byte(device_t dev)
{
unsigned device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4));
return do_smbus_recv_byte(res->base, device);
}
static int lsmbus_recv_byte(device_t dev)
{
u32 device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x90);
return do_smbus_recv_byte(res->base, device);
}
static void iommu_set_resources(device_t dev)
{
struct resource *res;
pci_dev_set_resources(dev);
res = find_resource(dev, 0x44);
/* Remember this resource has been stored */
res->flags |= IORESOURCE_STORED;
/* For now, do only 32-bit space allocation */
pci_write_config32(dev, 0x48, 0x0);
pci_write_config32(dev, 0x44, res->base | (1 << 0));
}
static int lsmbus_send_byte(device_t dev, uint8_t val)
{
unsigned device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x90);
return do_smbus_send_byte(res->base, device, val);
}
