/* read 0xa000-0xbfff */
BYTE REGPARM1 vic_fp_blk5_read(WORD addr)
{
if (ram5_flop) {
return cart_ram[addr & 0x1fff];
} else {
return flash040core_read(&flash_state, (addr & 0x1fff) | (cart_rom_bank << 13));
}
}
/* read 0x9c00-0x9fff */
static BYTE vic_um_io3_read(WORD addr)
{
ultimem_io3.io_source_valid = 0;
if (CART_CFG_DISABLE) {
/* Implement the state machine for re-enabling the register. */
switch (addr) {
case 0x355: /* Access 0x9f55 */
/* Advance the state if this is the 1st access, else reset. */
ultimem[16] = ultimem[16] == 0 ? 1 : 0;
break;
case 0x3aa: /* Access 0x9faa */
/* Advance the state if this is the 2nd access, else reset. */
ultimem[16] = ultimem[16] == 1 ? 2 : 0;
break;
case 0x301: /* Access 0x9f01 */
/* Advance the state if this is the 3rd access, else reset. */
if (ultimem[16] == 2)
ultimem[0] &= ~ultimem_reg0_regs_disable;
ultimem[16] = 0;
break;
default:
if (addr < 0x300)
break;
/* Accessing 0x9f00..0x9fff resets the state machine. */
ultimem[16] = 0;
}
if (addr >= 0x3f0)
return vic20_v_bus_last_data;
} else if (addr >= 0x3f0) {
ultimem_io3.io_source_valid = 1;
return ultimem[addr & 0xf];
}
switch (CART_CFG_IO(3)) {
case BLK_STATE_DISABLED:
break;
case BLK_STATE_ROM:
ultimem_io3.io_source_valid = 1;
return flash040core_read(&flash_state,
((addr | 0x1c00) + CART_IO_ADDR) &
(cart_rom_size - 1));
case BLK_STATE_RAM_RO:
case BLK_STATE_RAM_RW:
ultimem_io3.io_source_valid = 1;
return cart_ram[((addr | 0x1c00) + CART_IO_ADDR) &
(cart_ram_size - 1)];
}
return vic20_v_bus_last_data;
}
/* read 0xa000-0xbfff */
BYTE vic_um_blk5_read(WORD addr)
{
switch (CART_CFG_BLK(4)) {
case BLK_STATE_DISABLED:
return vic20_v_bus_last_data;
case BLK_STATE_ROM:
return flash040core_read(&flash_state,
((addr & 0x1fff) + CART_BLK_ADDR(4)) &
(cart_rom_size - 1));
case BLK_STATE_RAM_RO:
case BLK_STATE_RAM_RW:
return cart_ram[((addr & 0x1fff) + CART_BLK_ADDR(4)) &
(cart_ram_size - 1)];
}
return 0;
}
/* read 0x9800-0x9bff */
static BYTE vic_um_io2_read(WORD addr)
{
ultimem_io2.io_source_valid = 0;
switch (CART_CFG_IO(2)) {
case BLK_STATE_DISABLED:
break;
case BLK_STATE_ROM:
ultimem_io2.io_source_valid = 1;
return flash040core_read(&flash_state,
((addr | 0x1800) + CART_IO_ADDR) &
(cart_rom_size - 1));
case BLK_STATE_RAM_RO:
case BLK_STATE_RAM_RW:
ultimem_io2.io_source_valid = 1;
return cart_ram[((addr | 0x1800) + CART_IO_ADDR) &
(cart_ram_size - 1)];
}
return vic20_v_bus_last_data;
}
BYTE easyflash_romh_read(WORD addr)
{
return flash040core_read(easyflash_state_high, (easyflash_register_00 * 0x2000) + (addr & 0x1fff));
}
static BYTE internal_read(WORD addr, int blk, WORD base, int sel)
{
BYTE mode;
int bank;
unsigned int faddr;
BYTE value;
mode = register_a & REGA_MODE_MASK;
/* Determine which bank to access */
switch (mode) {
case MODE_FLASH:
case MODE_SUPER_ROM:
case MODE_SUPER_RAM:
bank = register_a & REGA_BANK_MASK;
break;
case MODE_ROM_RAM:
case MODE_RAM1:
bank = 1;
break;
case MODE_RAM2:
if (sel) {
bank = 2;
} else {
bank = 1;
}
break;
default:
bank = 0;
break;
}
/* Calculate Address */
faddr = calc_addr(addr, bank, base);
/* Perform access */
switch (mode) {
case MODE_START:
if (blk == 5) {
value = flash040core_read(&flash_state, faddr);
} else {
value = vic20_cpu_last_data;
}
break;
case MODE_FLASH:
case MODE_SUPER_ROM:
value = flash040core_read(&flash_state, faddr);
break;
case MODE_ROM_RAM:
if (sel) {
value = flash040core_read(&flash_state, faddr);
} else {
value = cart_ram[faddr];
}
break;
case MODE_RAM1:
case MODE_RAM2:
case MODE_SUPER_RAM:
value = cart_ram[faddr];
break;
default:
value = vic20_cpu_last_data;
break;
}
return value;
}