static void setupFlash(void) {
flash_enable_prefetch();
#ifdef _BOARD_SAFECAST_H_
flash_set_latency(FLASH_WAIT_STATE_1); // we run at 36 MHz
#else
flash_set_latency(FLASH_WAIT_STATE_2); // 2 wait states for 72 MHz
#endif
}
__weak void board_setup_flash(void) {
// Turn on as many Flash "go faster" features as
// possible. flash_enable_features() just ignores any flags it
// can't support.
flash_enable_features(FLASH_PREFETCH | FLASH_ICACHE | FLASH_DCACHE);
// FLASH_SAFE_WAIT_STATES is a hack that needs to go away.
flash_set_latency(FLASH_SAFE_WAIT_STATES);
}
static void setup_flash(void) {
// Turn on as many Flash "go faster" features as
// possible. flash_enable_features() just ignores any flags it
// can't support.
flash_enable_features(FLASH_PREFETCH | FLASH_ICACHE | FLASH_DCACHE);
// Configure the wait states, assuming we're operating at "close
// enough" to 3.3V.
flash_set_latency(FLASH_SAFE_WAIT_STATES);
}
void clk_rcfg_devices(void)
{
flash_set_latency(clk_get_bus_freq(CLK_FLASH));
return;
}
static void setupFlash(void) {
flash_enable_prefetch();
flash_set_latency(FLASH_WAIT_STATE_2);
}
void platform_init()
{
// Enable watchdog if requested
if (platform_should_start_watchdog && platform_should_start_watchdog())
{
watchdog_enable(WATCHDOG_DIVIDER_256, 0xFFF);
}
// Enable floating point
*cm3_scb_get_CPACR() |= 0xF << 20; /* set CP10 and CP11 Full Access */
// Enable syscfg
rcc_apb_enable(RCC_APB_BUS_SYSCFG, RCC_APB_BIT_SYSCFG);
// At reset, HCLK is 16MHz, set flash latency to 5 wait state to handle 168MHz
flash_set_latency(5);
// Configure PLL to have 336MHz VCO, then 48MHz for USB and 168 MHz for sysclk
rcc_pll_enable(RCC_PLL_SOURCE_HSI, 8, 168, RCC_PLL_MAIN_DIV_2, 7);
// Now SYSCLK is at 168MHz, set AHB divider to 1, APB1 to 4 and APB2 to 4
/*
* The frequency of the AHB domain is 168 MHz.
* The frequency of the APBx domain is 42 MHz.
*/
rcc_sysclk_set_prescalers(RCC_SYSCLK_AHB_PRE_1, RCC_SYSCLK_APB_PRE_4,
RCC_SYSCLK_APB_PRE_4);
// Select PLL as SYSCLK source clock
rcc_sysclk_select_source(RCC_SYSCLK_SOURCE_PLL);
// Setup the drivers
platform_drivers_setup();
// Setup the LEDs
platform_leds_setup();
// Setup the libraries
platform_lib_setup();
// Setup the peripherals
platform_periph_setup();
// Setup the net stack
platform_net_setup();
// Feed the random number generator
random_init(uid->uid32[2]);
log_printf(
"HCLK @%uMHz, SYSTICK @%uMHz", rcc_sysclk_get_clock_frequency(RCC_SYSCLK_CLOCK_HCLK) / 1000000,
rcc_sysclk_get_clock_frequency(RCC_SYSCLK_CLOCK_SYSTICK_CLK) / 1000000);
log_printf("\n\nPlatform starting in ");
uint32_t i;
for (i = 1; i > 0; i--)
{
log_printf("%u... ", i);
soft_timer_delay_s(1);
}
log_printf("\nGO!\n");
}
