int i2c_probe (uchar chip) { int res = 1; /* default = fail */ if (chip == inw (I2C_OA)) { return res; } /* wait until bus not busy */ wait_for_bb (); /* try to read one byte */ outw (1, I2C_CNT); /* set slave address */ outw (chip, I2C_SA); /* stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); /* enough delay for the NACK bit set */ udelay (50000); if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); outw(0xFFFF, I2C_STAT); } else { outw(0xFFFF, I2C_STAT); /* failue, clear sources*/ outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); outw (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ outw(0xFFFF, I2C_STAT); return res; }
int i2c_probe (uchar chip) { int res = 1; /* default = fail */ if (chip == readw (&i2c_base->oa)) { return res; } /* wait until bus not busy */ wait_for_bb (); /* try to read one byte */ writew (1, &i2c_base->cnt); /* set slave address */ writew (chip, &i2c_base->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); /* enough delay for the NACK bit set */ udelay (50000); if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); writew(0xFFFF, &i2c_base->stat); } else { writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/ writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/ writew(0xFFFF, &i2c_base->stat); return res; }
void i2c_init (int speed, int slaveadd) { u16 scl; outw(0x2, I2C_SYSC); /* for ES2 after soft reset */ udelay(1000); outw(0x0, I2C_SYSC); /* will probably self clear but */ if (inw (I2C_CON) & I2C_CON_EN) { outw (0, I2C_CON); udelay (50000); } /* 12Mhz I2C module clock */ outw (0, I2C_PSC); speed = speed/1000; /* 100 or 400 */ scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ outw (scl, I2C_SCLL); outw (scl, I2C_SCLH); /* own address */ outw (slaveadd, I2C_OA); outw (I2C_CON_EN, I2C_CON); /* have to enable intrrupts or OMAP i2c module doesn't work */ outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); udelay (1000); flush_fifo(); outw (0xFFFF, I2C_STAT); outw (0, I2C_CNT); }
static void rockchip_spi_handle_err(struct spi_master *master, struct spi_message *msg) { unsigned long flags; struct rockchip_spi *rs = spi_master_get_devdata(master); spin_lock_irqsave(&rs->lock, flags); /* * For DMA mode, we need terminate DMA channel and flush * fifo for the next transfer if DMA thansfer timeout. * handle_err() was called by core if transfer failed. * Maybe it is reasonable for error handling here. */ if (rs->use_dma) { if (rs->state & RXBUSY) { dmaengine_terminate_async(rs->dma_rx.ch); flush_fifo(rs); } if (rs->state & TXBUSY) dmaengine_terminate_async(rs->dma_tx.ch); } spin_unlock_irqrestore(&rs->lock, flags); }
int i2c_probe (uint8_t chip) { uint16_t status; int res = 1; /* default = fail */ if (chip == readw (&i2c_base->oa)) { return res; } /* wait until bus not busy */ wait_for_bb (); /* try to write one byte */ writew (1, &i2c_base->cnt); /* set slave address */ writew (chip, &i2c_base->sa); /* stop bit needed here */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); status = wait_for_pin(); /* check for ACK (!NAK) */ if (!(status & I2C_STAT_NACK)) res = 0; /* abort transfer (force idle state) */ writew(0, &i2c_base->con); flush_fifo(); writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/ writew(0xFFFF, &i2c_base->stat); return res; }
static int rockchip_spi_unprepare_message(struct spi_master *master, struct spi_message *msg) { unsigned long flags; struct rockchip_spi *rs = spi_master_get_devdata(master); spin_lock_irqsave(&rs->lock, flags); /* * For DMA mode, we need terminate DMA channel and flush * fifo for the next transfer if DMA thansfer timeout. * unprepare_message() was called by core if transfer complete * or timeout. Maybe it is reasonable for error handling here. */ if (rs->use_dma) { if (rs->state & RXBUSY) { dmaengine_terminate_all(rs->dma_rx.ch); flush_fifo(rs); } if (rs->state & TXBUSY) dmaengine_terminate_all(rs->dma_tx.ch); } spin_unlock_irqrestore(&rs->lock, flags); spi_enable_chip(rs, 0); return 0; }
int in_packet(pkt_t * p, uint32_t plen) { if (plen < 8) { LOG("PKTS: WARNING: got very short packet (len %d)\n", plen); return -1; } if ((p->hdr & PKT_MASK_VERSION) != VERSION << VERSION_SHIFT) { LOG("PKTS: WARNING: dropping pkt with invalid version, hdr %x\n", p->hdr); return -2; /* drop wrong version packets */ } if (plen < p->pkt_len ) { #if 0 /* this is fine -1 is the marker for incomplete packets */ LOG("PKTS: WARNING: got short packet (%d < %d)\n", plen, p->pkt_len ); #endif return -1; } if (p->pkt_len > FIFO_WIDTH) { LOG("PKTS: WARNING: got long packet (len %d)\n", plen); return -3; } switch(p->hdr & PKT_MASK_TYPE) { case PKT_TYPE_SET_SCREEN_BLK: case PKT_TYPE_SET_SCREEN_WHT: case PKT_TYPE_SET_SCREEN_RND_BW: case PKT_TYPE_SET_SCREEN_RND_COL: case PKT_TYPE_SET_FRAME_RATE: case PKT_TYPE_SET_FADE_RATE: case PKT_TYPE_SET_DURATION: case PKT_TYPE_SET_PIXEL: case PKT_TYPE_SET_SCREEN: case PKT_TYPE_FLIP_DBL_BUF: case PKT_TYPE_TEXT: case PKT_TYPE_SET_FONT: wr_fifo(p); break; /* out-of-band immediate commands follow */ case PKT_TYPE_FLUSH_FIFO: flush_fifo(); break; case PKT_TYPE_SHUTDOWN: gigargoyle_shutdown(); /* FIXME only from QM, not from IS */ break; default: return 0; /* drop unsupported packages */ } return 0; }
int i2c_probe(uchar chip) { int res = 1; /* default = fail */ u32 status; if (chip == readw ((i2c_base + I2C_OA_OFS))) return res; /* wait until bus not busy */ status = wait_for_bb(); /* exiting on BUS busy */ if (status & I2C_TIMEOUT) return res; /* try to read one byte */ writew (1, (i2c_base + I2C_CNT_OFS)); /* set slave address */ writew (chip, (i2c_base + I2C_SA_OFS)); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, (i2c_base + I2C_CON_OFS)); /* enough delay for the NACK bit set */ udelay (50000); if (!(readw ((i2c_base + I2C_STAT_OFS)) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); writew(0xFFFF, (i2c_base + I2C_STAT_OFS)); } else { writew(0xFFFF, (i2c_base + I2C_STAT_OFS)); /* failue, clear sources*/ /* finish up xfer */ writew(readw((i2c_base + I2C_CON_OFS)) | I2C_CON_STP, (i2c_base + I2C_CON_OFS)); udelay(20000); wait_for_bb(); status = wait_for_bb(); /* exiting on BUS busy */ if (status & I2C_TIMEOUT) return res; } flush_fifo(); /* don't allow any more data in...we don't want it.*/ writew(0, (i2c_base + I2C_CNT_OFS)); writew(0xFFFF, (i2c_base + I2C_STAT_OFS)); return res; }
int i2c_probe (uchar chip) { u16 status; int res = 1; /* default = fail */ if (chip == readw (&i2c_base->oa)) { return res; } /* wait until bus not busy */ wait_for_bb (); /* try to read one byte */ writew (1, &i2c_base->cnt); /* set slave address */ writew (chip, &i2c_base->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); while (1) { status = wait_for_pin(); if (status == 0 || status & I2C_STAT_AL) { res = 1; goto probe_exit; } if (status & I2C_STAT_NACK) { res = 1; writew(0xff, &i2c_base->stat); writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); wait_for_bb (); break; } if (status & I2C_STAT_ARDY) { writew(I2C_STAT_ARDY, &i2c_base->stat); break; } if (status & I2C_STAT_RRDY) { res = 0; #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ defined(CONFIG_OMAP44XX) readb(&i2c_base->data); #else readw(&i2c_base->data); #endif writew(I2C_STAT_RRDY, &i2c_base->stat); } } probe_exit: flush_fifo(); writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/ writew(0xFFFF, &i2c_base->stat); return res; }
static av_cold void uninit(AVFilterContext *ctx) { FPSContext *s = ctx->priv; if (s->fifo) { s->drop += av_fifo_size(s->fifo) / sizeof(AVFilterBufferRef*); flush_fifo(s->fifo); av_fifo_free(s->fifo); } av_log(ctx, AV_LOG_VERBOSE, "%d frames in, %d frames out; %d frames dropped, " "%d frames duplicated.\n", s->frames_in, s->frames_out, s->drop, s->dup); }
int chrif_send_report(char* buf, int len) { #ifndef STATS_OPT_OUT chrif_check(-1); WFIFOHEAD(char_fd,len + 2); WFIFOW(char_fd,0) = 0x3008; memcpy(WFIFOP(char_fd,2), buf, len); WFIFOSET(char_fd,len + 2); flush_fifo(char_fd); /* ensure it's sent now. */ #endif return 0; }
static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd, int *waitdelay) { int timeout = I2C_TIMEOUT; int deblock = 1; retry: if (readw(&i2c_base->con) & I2C_CON_EN) { writew(0, &i2c_base->con); udelay(50000); } writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ udelay(1000); writew(I2C_CON_EN, &i2c_base->con); while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { if (timeout <= 0) { puts("ERROR: Timeout in soft-reset\n"); return; } udelay(1000); } if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) { printf("ERROR: failed to setup I2C bus-speed!\n"); return; } /* own address */ writew(slaveadd, &i2c_base->oa); #if defined(CONFIG_OMAP34XX) /* * Have to enable interrupts for OMAP2/3, these IPs don't have * an 'irqstatus_raw' register and we shall have to poll 'stat' */ writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); #endif udelay(1000); flush_fifo(i2c_base); writew(0xFFFF, &i2c_base->stat); /* Handle possible failed I2C state */ if (wait_for_bb(i2c_base, *waitdelay)) if (deblock == 1) { omap24_i2c_deblock(i2c_base); deblock = 0; goto retry; } }
/** * vrrp_ctrl_read() - Read control fifo */ vrrp_event_t vrrp_ctrl_read(struct vrrp * vrrp, struct vrrp_net * vnet) { int readbytes = 0; readbytes = read(vrrp->ctrl.fd, vrrp->ctrl.msg, CTRL_MAXCHAR); if (readbytes > 0) { flush_fifo(vrrp->ctrl.fd); vrrp->ctrl.msg[CTRL_MAXCHAR - 1] = '\0'; return vrrp_ctrl_cmd(vrrp, vnet); } return INVALID; }
/* * i2c_probe: Use write access. Allows to identify addresses that are * write-only (like the config register of dual-port EEPROMs) */ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) { struct i2c *i2c_base = omap24_get_base(adap); u16 status; int res = 1; /* default = fail */ if (chip == readw(&i2c_base->oa)) return res; /* Wait until bus is free */ if (wait_for_bb(adap)) return res; /* No data transfer, slave addr only */ writew(chip, &i2c_base->sa); /* Stop bit needed here */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); status = wait_for_event(adap); if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { /* * With current high-level command implementation, notifying * the user shall flood the console with 127 messages. If * silent exit is desired upon unconfigured bus, remove the * following 'if' section: */ if (status == I2C_STAT_XRDY) printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n", adap->hwadapnr, status); goto pr_exit; } /* Check for ACK (!NAK) */ if (!(status & I2C_STAT_NACK)) { res = 0; /* Device found */ udelay(adap->waitdelay);/* Required by AM335X in SPL */ /* Abort transfer (force idle state) */ writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ udelay(1000); writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); /* STP */ } pr_exit: flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); return res; }
void chrif_send_report(char* buf, int len) { #ifndef STATS_OPT_OUT if( char_fd ) { WFIFOHEAD(char_fd,len + 2); WFIFOW(char_fd,0) = 0x3008; memcpy(WFIFOP(char_fd,2), buf, len); WFIFOSET(char_fd,len + 2); flush_fifo(char_fd); /* ensure it's sent now. */ } #endif }
static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) { int i2c_error = 0; u16 status, stat; /* wait until bus not busy */ wait_for_bb (); /* two bytes */ outw (2, I2C_CNT); /* set slave address */ outw (devaddr, I2C_SA); /* stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); /* wait until state change */ status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* send out two bytes */ outw ((value << 8) + regoffset, I2C_DATA); /* must have enough delay to allow BB bit to go low */ udelay (50000); if (inw (I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { int eout = 200; outw (I2C_CON_EN, I2C_CON); while ((stat = inw (I2C_STAT)) || (inw (I2C_CON) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ outw (0xFFFF, I2C_STAT); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); outw (0xFFFF, I2C_STAT); outw (0, I2C_CNT); return i2c_error; }
static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) { int i2c_error = 0; u16 status; /* wait until bus not busy */ wait_for_bb (); /* one byte only */ outw (1, I2C_CNT); /* set slave address */ outw (devaddr, I2C_SA); /* no stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); status = wait_for_pin (); if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ outw (0, I2C_CON); wait_for_bb (); /* set slave address */ outw (devaddr, I2C_SA); /* read one byte from slave */ outw (1, I2C_CNT); /* need stop bit here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { *value = inw (I2C_DRR); udelay (20000); } else { i2c_error = 1; } if (!i2c_error) { outw (I2C_CON_EN, I2C_CON); } } flush_fifo(); outw (0xFFFF, I2C_STAT); outw (0, I2C_CNT); return i2c_error; }
/* * i2c_abort - called when a I2C transaction failed */ static void i2c_abort(struct u5500_i2c_regs *i2c_regs) { #ifdef DEBUG print_abort_reason(i2c_regs); #endif /* flush RX and TX fifos */ flush_fifo(i2c_regs); /* Acknowledge the Master Transaction Done */ i2c_set_bit(&i2c_regs->icr, I2C_INT_MTD); /* Acknowledge the Master Transaction Done Without Stop */ i2c_set_bit(&i2c_regs->icr, I2C_INT_MTDWS); i2c_init(i2c_bus_speed[i2c_bus_num], CONFIG_SYS_I2C_SLAVE); }
// パーティ情報まとめ送り int mapif_party_info(int fd,struct party *p) { // unsigned char buf[1024]; //Because this packet is so big, allow for a larger buffer based on party max size. unsigned char buf[100+75*MAX_PARTY]; WBUFW(buf,0)=0x3821; memcpy(buf+4,p,sizeof(struct party)); WBUFW(buf,2)=4+sizeof(struct party); if(fd<0) { flush_fifos(); //This packet is BIG, so better have the socket buffers empty to allocate space for them. [Skotlex] mapif_sendall(buf,WBUFW(buf,2)); } else { flush_fifo(fd); mapif_send(fd,buf,WBUFW(buf,2)); } // printf("int_party: info %d %s\n",p->party_id,p->name); return 0; }
/* * Probe the given I2C chip address. Returns 0 if a chip responded, * not 0 on failure. */ int i2c_probe(uchar chip) { u32 mcr = 0; struct u5500_i2c_regs *i2c_regs; if (chip == CONFIG_SYS_I2C_SLAVE) return 1; i2c_regs = i2c_dev[i2c_bus_num]; /* Set the address mode to 7 bit */ WRITE_FIELD(mcr, I2C_MCR_AM, I2C_MCR_SHIFT_AM, 1); /* Store the slave address in the master control register */ WRITE_FIELD(mcr, I2C_MCR_A10, I2C_MCR_SHIFT_A7, chip); /* Read operation */ SET_BIT(mcr, I2C_MCR_OP); /* Set the frame length to one byte */ WRITE_FIELD(mcr, I2C_MCR_LENGTH, I2C_MCR_SHIFT_LENGTH, 1); /* Current transaction is terminated by STOP condition */ SET_BIT(mcr, I2C_MCR_STOP); /* Write MCR register */ writel(mcr, &i2c_regs->mcr); /* Wait until the Rx Fifo is not empty */ if (loop_till_bit_clear((void *)&i2c_regs->risr, I2C_INT_RXFE, I2C_ENDAD_COUNTER)) { i2c_abort(i2c_regs); return -1; } flush_fifo(i2c_regs); /* Acknowledge the Master Transaction Done */ i2c_set_bit(&i2c_regs->icr, I2C_INT_MTD); /* Acknowledge the Master Transaction Done Without Stop */ i2c_set_bit(&i2c_regs->icr, I2C_INT_MTDWS); return 0; }
static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) { int i2c_error = 0; u16 status, stat; u16 temp; /* wait until bus not busy */ wait_for_bb (); /* two bytes */ outw (2, I2C_CNT); /* set slave address */ outw (devaddr, I2C_SA); /* stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); /* wait until state change */ status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* send out two bytes */ outw (value, I2C_DXR); /* must have enough delay to allow BB bit to go low */ udelay (50000); if (inw (I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { outw (I2C_CON_EN, I2C_CON); do { temp = inw(I2C_STAT) && I2C_STAT_SCD; } while (!temp); } flush_fifo(); outw (0xFFFF, I2C_STAT); outw (0, I2C_CNT); return i2c_error; }
static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { struct i2c *i2c_base = omap24_get_base(adap); int timeout = I2C_TIMEOUT; if (readw(&i2c_base->con) & I2C_CON_EN) { writew(0, &i2c_base->con); udelay(50000); } writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ udelay(1000); writew(I2C_CON_EN, &i2c_base->con); while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { if (timeout <= 0) { puts("ERROR: Timeout in soft-reset\n"); return; } udelay(1000); } if (0 != omap24_i2c_setspeed(adap, speed)) { printf("ERROR: failed to setup I2C bus-speed!\n"); return; } /* own address */ writew(slaveadd, &i2c_base->oa); #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* * Have to enable interrupts for OMAP2/3, these IPs don't have * an 'irqstatus_raw' register and we shall have to poll 'stat' */ writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); #endif udelay(1000); flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); }
static int i2c_multidata_write_byte(u8 devaddr, u8 regoffset, u8 *values, int len) { int eout; int i2c_error = 0; u16 status, stat; int i=0; int count=0; /* wait until bus not busy */ wait_for_bb(); //printf("I2C DEBUG: Bus not busy complete\n"); count = len + 1; /* length+1 bytes */ outw(count, I2C_CNT); //printf("I2C DEBUG: Count set to %x\n", count); /* set slave address */ outw(devaddr, I2C_SA); //printf("I2C DEBUG: Slave Address set to %x\n", devaddr); /* stop bit needed here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); //printf("I2C DEBUG: Configuration set\n"); /* wait until state change */ status = wait_for_pin(); //printf("I2C DEBUG: Wait pin status change\n"); if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) /* send out 1 byte */ //printf("I2C DEBUG: Transmit ready status\n"); outb(regoffset, I2C_DATA); //printf("I2C DEBUG: Register Offset set to %x\n", regoffset); outw(I2C_STAT_XRDY, I2C_STAT); //printf("I2C DEBUG: Clearing transmit ready\n"); for (i = 0; i < len; i++) { status = wait_for_pin(); //printf("I2C DEBUG: Wait pin status change\n"); if ((status & I2C_STAT_XRDY)) { //printf("I2C DEBUG: Data output iteration %x\n", i); /* send out next 1 byte */ outb(values[i], I2C_DATA); //printf("I2C DEBUG: Data output value written %x\n", values[i]); outw(I2C_STAT_XRDY, I2C_STAT); //printf("I2C DEBUG: Clearing transmit ready \n"); } else { printf("I2C error\n"); i2c_error = 1; } } //printf("I2C DEBUG: Multidata byte write transfer complete \n"); #else /* send out 2 bytes */ outw((value << 8) | regoffset, I2C_DATA); #endif /* must have enough delay to allow BB bit to go low */ eout= 20000; while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && eout--) ; if (eout <= 0) printf("timed out in i2c_write_byte: I2C_STAT=%x\n", inw(I2C_STAT)); if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { eout = 2000; outw(I2C_CON_EN, I2C_CON); while ((stat = inw(I2C_STAT)) || (inw(I2C_CON) & I2C_CON_MST)) { /* have to read to clear intrrupt */ outw(0xFFFF, I2C_STAT); if (--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }
int i2c_read_2_byte(u8 devaddr, u8 regoffset, u8 * value) { int err; int i2c_error = 0; u16 status; if (!value) return 1; /* wait until bus not busy */ wait_for_bb(); /* one byte only */ outw(1, I2C_CNT); /* set slave address */ outw(devaddr, I2C_SA); /* no stop bit needed here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); status = wait_for_pin(); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ outb(regoffset, I2C_DATA); /* Important: wait for ARDY bit to set */ err = 2000; while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && err--) ; if (err <= 0) i2c_error = 1; if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { err = 2000; outw(I2C_CON_EN, I2C_CON); while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { /* Have to clear pending interrupt to clear I2C_STAT */ outw(0xFFFF, I2C_STAT); if (!err--) { break; } } /* set slave address */ outw(devaddr, I2C_SA); /* read two bytes from slave */ outw(2, I2C_CNT); /* need stop bit here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); status = wait_for_pin(); if (status & I2C_STAT_RRDY) { int i =0; for (i=0; i<2; i++) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) *value++ = inb(I2C_DATA); #else *value = inw(I2C_DATA); #endif /* Important: wait for ARDY bit to set */ err = 20000; while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && err--); } if (err <= 0){ printf("i2c_read_byte -- I2C_STAT_ARDY error\n"); i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { int err = 1000; outw(I2C_CON_EN, I2C_CON); while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { outw(0xFFFF, I2C_STAT); if (!err--) { break; } } } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }
static int i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) { int i2c_error = 0; u16 status, stat; /* wait until bus not busy */ wait_for_bb(); /* two bytes */ outw(2, I2C_CNT); /* set slave address */ outw(devaddr, I2C_SA); /* stop bit needed here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); /* wait until state change */ status = wait_for_pin(); if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) /* send out 1 byte */ outb(regoffset, I2C_DATA); outw(I2C_STAT_XRDY, I2C_STAT); status = wait_for_pin(); if ((status & I2C_STAT_XRDY)) { /* send out next 1 byte */ outb(value, I2C_DATA); outw(I2C_STAT_XRDY, I2C_STAT); } else { i2c_error = 1; } #else /* send out 2 bytes */ outw((value << 8) | regoffset, I2C_DATA); #endif /* must have enough delay to allow BB bit to go low */ udelay(50000); if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { int eout = 200; outw(I2C_CON_EN, I2C_CON); while ((stat = inw(I2C_STAT)) || (inw(I2C_CON) & I2C_CON_MST)) { udelay(1000); /* have to read to clear intrrupt */ outw(0xFFFF, I2C_STAT); if (--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }
static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 * value) { int i2c_error = 0; u16 status; /* wait until bus not busy */ wait_for_bb(); /* one byte only */ outw(1, I2C_CNT); /* set slave address */ outw(devaddr, I2C_SA); /* no stop bit needed here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); status = wait_for_pin(); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ outb(regoffset, I2C_DATA); udelay(20000); if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { int err = 10; while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { udelay(10000); /* Have to clear pending interrupt to clear I2C_STAT */ outw(0xFFFF, I2C_STAT); if (!err--) { break; } } /* set slave address */ outw(devaddr, I2C_SA); /* read one byte from slave */ outw(1, I2C_CNT); /* need stop bit here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); status = wait_for_pin(); if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) *value = inb(I2C_DATA); #else *value = inw(I2C_DATA); #endif udelay(20000); } else { i2c_error = 1; } if (!i2c_error) { int err = 10; outw(I2C_CON_EN, I2C_CON); while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { udelay(10000); outw(0xFFFF, I2C_STAT); if (!err--) { break; } } } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }
void i2c_init(int speed, int slaveadd) { int scl_lh = 0; int psc = 0; int iclk = 0; int reset_timeout = 10; /* assume clock settings done */ /* write to clock regs to enable if and fun clks for board */ #if defined(CONFIG_OMAP243X) { u32 v = 0; v = __raw_readl(CM_ICLKEN1_CORE) | (0x3 << 19); /* Interface clocks on */ __raw_writel(v, CM_ICLKEN1_CORE); v = __raw_readl(CM_FCLKEN1_CORE) & ~(0x3 << 19); __raw_writel(v, CM_FCLKEN1_CORE); v = __raw_readl(CM_FCLKEN2_CORE) | (0x3 << 19); /* Functional Clocks on */ __raw_writel(v, CM_FCLKEN2_CORE); } #endif /* End of 243x code */ if (inw(I2C_CON) & I2C_CON_EN) { outw(0, I2C_CON); udelay(50000); } outw(I2C_SYSC_SRST, I2C_SYSC); /* for ES2 after soft reset */ udelay(1000); /* compute divisors - dynamic decision based on i/p clock */ psc = I2C_PSC_MAX; while (psc >= I2C_PSC_MIN) { iclk = I2C_IP_CLK / (psc + 1); switch (speed) { case OMAP_I2C_STANDARD: scl_lh = (iclk * 10 / (OMAP_I2C_STANDARD * 2)); break; case OMAP_I2C_HIGH_SPEED: /* PSC ignored for HS */ case OMAP_I2C_FAST_MODE: scl_lh = (iclk * 10 / (OMAP_I2C_FAST_MODE * 2)); break; /* no default case - fall thru */ } DBG("Search- speed= %d SysClk=%d, iclk=%d,psc=0x%x[%d],scl_lh=0x%x[%d]\n", speed, I2C_IP_CLK, iclk, psc, psc, scl_lh, scl_lh); /* Check for decimal places.. if yes, we ignore it */ if (scl_lh % 10) { scl_lh = -1; } else { scl_lh /= 10; scl_lh -= 7; } if (scl_lh >= 0) { break; } psc--; } /* Did not find an optimal config */ if (psc < I2C_PSC_MIN) { printf ("Unable to set Prescalar for i2c_clock=%d syI2C_IP_CLK=%d\n", speed, I2C_IP_CLK); psc = 0; return; } iclk = I2C_IP_CLK / (psc + 1); /* Initialize the I2C clock timers to generate an I2C bus clock * frequency of i2c_clock kilohertz (default is 100 KHz). */ switch (speed) { case OMAP_I2C_STANDARD: scl_lh = (((iclk / (OMAP_I2C_STANDARD * 2)) - 7) & I2C_SCLL_SCLL_M) << I2C_SCLL_SCLL; break; case OMAP_I2C_HIGH_SPEED: scl_lh = (((I2C_IP_CLK / (OMAP_I2C_HIGH_SPEED * 2)) - 7) & I2C_SCLH_HSSCLL_M) << I2C_SCLL_HSSCLL; /* Fall through for the FS settings */ case OMAP_I2C_FAST_MODE: scl_lh |= (((iclk / (OMAP_I2C_FAST_MODE * 2)) - 7) & I2C_SCLL_SCLL_M) << I2C_SCLL_SCLL; break; /* no default case */ } DBG(" speed= %d SysClk=%d, iclk=%d,psc=0x%x[%d],scl_lh=0x%x[%d]\n", speed, I2C_IP_CLK, iclk, psc, psc, scl_lh, scl_lh); outw(I2C_CON_EN, I2C_CON); while (!(inw(I2C_SYSS) & I2C_SYSS_RDONE) && reset_timeout--) { if (reset_timeout <= 0) printf("ERROR: Timeout while waiting for soft-reset to complete\n"); udelay(1000); } outw(0, I2C_CON); /* Disable I2C controller before writing to PSC and SCL registers */ outw(psc, I2C_PSC); outw(scl_lh, I2C_SCLL); outw(scl_lh, I2C_SCLH); /* own address */ outw(slaveadd, I2C_OA); outw(I2C_CON_EN, I2C_CON); /* have to enable intrrupts or OMAP i2c module doesn't work */ outw(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); udelay(1000); flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); i2c_speed = speed; }
static int filter_frame(AVFilterLink *inlink, AVFrame *buf) { AVFilterContext *ctx = inlink->dst; FPSContext *s = ctx->priv; AVFilterLink *outlink = ctx->outputs[0]; int64_t delta; int i, ret; s->frames_in++; /* discard frames until we get the first timestamp */ if (s->pts == AV_NOPTS_VALUE) { if (buf->pts != AV_NOPTS_VALUE) { ret = write_to_fifo(s->fifo, buf); if (ret < 0) return ret; s->first_pts = s->pts = buf->pts; } else { av_log(ctx, AV_LOG_WARNING, "Discarding initial frame(s) with no " "timestamp.\n"); av_frame_free(&buf); s->drop++; } return 0; } /* now wait for the next timestamp */ if (buf->pts == AV_NOPTS_VALUE) { return write_to_fifo(s->fifo, buf); } /* number of output frames */ delta = av_rescale_q(buf->pts - s->pts, inlink->time_base, outlink->time_base); if (delta < 1) { /* drop the frame and everything buffered except the first */ AVFrame *tmp; int drop = av_fifo_size(s->fifo)/sizeof(AVFrame*); av_log(ctx, AV_LOG_DEBUG, "Dropping %d frame(s).\n", drop); s->drop += drop; av_fifo_generic_read(s->fifo, &tmp, sizeof(tmp), NULL); flush_fifo(s->fifo); ret = write_to_fifo(s->fifo, tmp); av_frame_free(&buf); return ret; } /* can output >= 1 frames */ for (i = 0; i < delta; i++) { AVFrame *buf_out; av_fifo_generic_read(s->fifo, &buf_out, sizeof(buf_out), NULL); /* duplicate the frame if needed */ if (!av_fifo_size(s->fifo) && i < delta - 1) { AVFrame *dup = av_frame_clone(buf_out); av_log(ctx, AV_LOG_DEBUG, "Duplicating frame.\n"); if (dup) ret = write_to_fifo(s->fifo, dup); else ret = AVERROR(ENOMEM); if (ret < 0) { av_frame_free(&buf_out); av_frame_free(&buf); return ret; } s->dup++; } buf_out->pts = av_rescale_q(s->first_pts, inlink->time_base, outlink->time_base) + s->frames_out; if ((ret = ff_filter_frame(outlink, buf_out)) < 0) { av_frame_free(&buf); return ret; } s->frames_out++; } flush_fifo(s->fifo); ret = write_to_fifo(s->fifo, buf); s->pts = s->first_pts + av_rescale_q(s->frames_out, outlink->time_base, inlink->time_base); return ret; }
void flush_fifos(void) { int i; for(i = 1; i < fd_max; i++) flush_fifo(i); }
int generic_i2c_write(u8 devaddr, u8 *value, u8 len) { int eout = 500; int i2c_error = 0; u16 status, stat; u8 i = 0; /* wait until bus not busy */ wait_for_bb(); /* <len> bytes */ outw(len, I2C_CNT); /* set slave address */ outw(devaddr, I2C_SA); /* stop bit needed here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); for (i = 0; (i < len) && (!i2c_error); i++) { /* wait until state change */ status = wait_for_pin(); if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) /* send out 1 byte */ outb(value[i], I2C_DATA); #endif } else { i2c_error = 1; } } if (i2c_error) { printf("I2C read: I/O error\n"); } else { printf("done\n"); } /* must have enough delay to allow BB bit to go low */ while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && eout--) udelay(100); if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } if (!i2c_error) { eout = 200; outw(I2C_CON_EN, I2C_CON); while ((stat = inw(I2C_STAT)) || (inw(I2C_CON) & I2C_CON_MST)) { udelay(1000); /* have to read to clear intrrupt */ outw(0xFFFF, I2C_STAT); if (--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }