static void sdk7786_power_off(void) { fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR); /* * It can take up to 20us for the R8C to do its job, back off and * wait a bit until we've been shut off. Even though newer FPGA * versions don't set the ACK bit, the latency issue remains. */ while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0) cpu_sleep(); }
static int __init sdk7786_pci_init(void) { u16 data = fpga_read_reg(PCIECR); /* * Enable slot #4 if it's been specified on the command line. * * Optionally reroute if slot #4 has a card present while slot #3 * does not, regardless of command line value. * * Card presence is logically inverted. */ slot4en ?: (!(data & PCIECR_PRST4) && (data & PCIECR_PRST3)); if (slot4en) { pr_info("Activating PCIe slot#4 (disabling slot#3)\n"); data &= ~PCIECR_PCIEMUX1; fpga_write_reg(data, PCIECR); /* Warn about forced rerouting if slot#3 is occupied */ if ((data & PCIECR_PRST3) == 0) { pr_warning("Unreachable card detected in slot#3\n"); return -EBUSY; } } else pr_info("PCIe slot#4 disabled\n"); return 0; }
void __init sdk7786_fpga_init(void) { u16 version, date; sdk7786_fpga_base = sdk7786_fpga_probe(); if (unlikely(!sdk7786_fpga_base)) { panic("FPGA detection failed.\n"); return; } version = fpga_read_reg(FPGAVR); date = fpga_read_reg(FPGADR); pr_info("\tFPGA version:\t%d.%d (built on %d/%d/%d)\n", bcd2bin(version >> 8) & 0xf, bcd2bin(version & 0xf), ((date >> 12) & 0xf) + 2000, (date >> 8) & 0xf, bcd2bin(date & 0xff)); }
/* Initialize the board */ static void __init sdk7786_setup(char **cmdline_p) { pr_info("Renesas Technology Europe SDK7786 support:\n"); sdk7786_fpga_init(); pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf); machine_ops.restart = sdk7786_restart; pm_power_off = sdk7786_power_off; register_smp_ops(&shx3_smp_ops); }
static int sdk7786_i2c_setup(void) { unsigned int tmp; /* * Hand over I2C control to the FPGA. */ tmp = fpga_read_reg(SBCR); tmp &= ~SCBR_I2CCEN; tmp |= SCBR_I2CMEN; fpga_write_reg(tmp, SBCR); return i2c_register_board_info(0, sdk7786_i2c_devices, ARRAY_SIZE(sdk7786_i2c_devices)); }
static int usrgpir_gpio_get(struct gpio_chip *chip, unsigned gpio) { return !!(fpga_read_reg(USRGPIR) & (1 << gpio)); }
void main_loop() { if (first) { first = FALSE; printf("main_loop CPUCS = 0x%x\r\n", CPUCS); } /* check for ep1 out data */ if(!(EP1OUTCS & bmEPBUSY)) { BYTE *buf_out = EP1OUTBUF; BYTE *buf_in = EP1INBUF; BYTE len_out = EP1OUTBC; BYTE len_in = 0; BOOL ok = FALSE; //printf("ep1 out\r\n"); /* decrypt data */ ep1_decrypt(buf_out, buf_out, len_out); /* handle command */ //if (buf_out[0] != CMD_FPGA_UPLOAD_DATA) // printf("cmd 0x%x len %d\r\n", buf_out[0], len_out); switch (buf_out[0]) { case CMD_WRITE_EEPROM: if (len_out > 5 && buf_out[1] == 0x42 && buf_out[2] == 0x55 && (buf_out[4] + 5) == len_out && eeprom_write(I2C_EEPROM_ADDRESS, buf_out[3], buf_out[4], buf_out + 5)) { ok = TRUE; } break; case CMD_READ_EEPROM: if (len_out == 5 && buf_out[1] == 0x33 && buf_out[2] == 0x81) { /* wait for ep1in ready */ while (EP1INCS & bmEPBUSY); if (eeprom_read(I2C_EEPROM_ADDRESS, buf_out[3], buf_out[4], buf_in)) { len_in = buf_out[4]; ok = TRUE; } } break; case CMD_WRITE_LED_TABLE: if (len_out > 3 && (buf_out[2] + 3) == len_out && buf_out[1] < sizeof (led_table)) { BYTE *dst = led_table + buf_out[1]; BYTE *src = buf_out + 3; BYTE len = buf_out[2]; while (len-- > 0) { *dst++ = *src++; if (dst == led_table + sizeof (led_table)) dst = led_table; } ok = TRUE; } break; case CMD_SET_LED_MODE: if (len_out == 6) { led_run = buf_out[1]; RCAP2L = buf_out[2]; RCAP2H = buf_out[3]; led_div = buf_out[4]; led_repeat = buf_out[5]; ok = TRUE; } break; case CMD_FPGA_UPLOAD_INIT: ok = fpga_upload_init(); break; case CMD_FPGA_UPLOAD_DATA: if (len_out > 2 && (buf_out[1] + 2) == len_out) { ok = fpga_upload_data(buf_out + 2, buf_out[1]); } break; case CMD_FPGA_WRITE_REGISTER: if (len_out > 2 && (2*buf_out[1] + 2) == len_out) { BYTE i; for (i = 0; i < buf_out[1]; i++) fpga_write_reg(buf_out[2 + 2*i], buf_out[2 + 2*i + 1]); ok = TRUE; } break; case CMD_FPGA_READ_REGISTER: if (len_out > 2 && (buf_out[1] + 2) == len_out) { BYTE i; /* wait for ep1in ready */ while (EP1INCS & bmEPBUSY); for (i = 0; i < buf_out[1]; i++) buf_in[i] = fpga_read_reg(buf_out[2 + i]); len_in = buf_out[1]; ok = TRUE; } break; case CMD_START_ACQUISITION: if (len_out == 1) { gpif_stuff_start(); ok = TRUE; } break; case CMD_ABORT_ACQUISITION_ASYNC: if (len_out == 1) { gpif_stuff_abort(); ok = TRUE; } break; case CMD_ABORT_ACQUISITION_SYNC: if (len_out == 2) { gpif_stuff_abort(); /* wait for ep1in ready */ while (EP1INCS & bmEPBUSY); buf_in[0] = buf_out[1] ^ 0xff; len_in = 1; ok = TRUE; } break; // CMD_RETURN_TO_BOOTLOADER 0x7c // CMD_GET_REVID 0x82 } if (!ok) { /* stall ep1 */ EP1OUTCS |= bmEPSTALL; /* FIXME: dont stall? */ printf("STALL\r\n"); } else if (len_in > 0) { /* send reply */ ep1_encrypt(buf_in, buf_in, len_in); SYNCDELAY; EP1INBC = len_in; } /* prepare ep1 out for next packet */ EP1OUTBC = 0xff; SYNCDELAY; } /* led stuff */ if (TF2) { static BYTE count = 0, index = 0; CLEAR_TIMER2(); if (led_run) { if (count == 0) { count = led_div; if (index < sizeof (led_table)) fpga_write_reg(5, led_table[index++]); if (index == sizeof (led_table) && led_repeat) index = 0; } else { count -= 1; } } } }
int main(void) { uint32_t REVID_reg=HWREG(SYSCONFIG_REG_BASE); if(REVID_reg!=0x4E840102) { printf("fail to read revid ,error debug "); SW_BREAKPOINT ; return 1; } dsp_delay(200); EMIF_init(); UPP_PINMUX(); test_fpga_reg(); // uint32_t bcnt= Loadfromfile(ptr); // int j=0; memset(recv_adc_buffer,0,UPP_RX_BCNT); TEST_uart(); // load_fpga(ptr,bcnt); init_9822(); fpga_upp_test(); config_upp(); int frcnt = 0; int cc=0; static int calc_cnt = 0; while(1) { config_upp(); calc_cnt++; recv_adc_buffer[2531]=1; upp_receive_fifo(recv_adc_buffer,UPP_RX_LNCNT,UPP_DMA_BCNT); cc=0; char show_str[50]; //送的数据速度太快,导致程序移植timeout, //好像和buffer一直没有被取出会导致overflow相关。如果程序不运行需要大量时间的函数就不会出现问题 while(1) { if(recv_adc_buffer[2531]!=1 ) { if (calc_cnt %loop_num ==1) { point_notclear = point_nclear_return_maxValue(recv_adc_buffer, 20, &MaxValue); leftpoint = bi_side_search_withMaxValue(recv_adc_buffer, point_notclear, 0, ratio, 5, MaxValue); rightpoint = bi_side_search_withMaxValue(recv_adc_buffer, point_notclear, 1, ratio, 5, MaxValue); Set_Zeros(buffer_int_data, leftpoint - 5, rightpoint + 5); Sum_To_Int(recv_adc_buffer, buffer_int_data, leftpoint - 5, rightpoint + 5); } else if(calc_cnt %loop_num != 0) { Sum_To_Int(recv_adc_buffer, buffer_int_data, leftpoint - 5, rightpoint + 5); //sprintf(show_str, "location = %d\t\t",frcnt); //str2com(show_str); } else { Sum_To_Int(recv_adc_buffer, buffer_int_data, leftpoint - 5, rightpoint + 5); //dsp_delay(500000); //Data_Average_Int(buffer_int_data, buffer_tmp , 4, 790, 850); region_gauss_filter(buffer_int_data, leftpoint - 5, rightpoint + 5,buffer_float_data); //point_notclear = point_nclear_return_maxValue(recv_adc_buffer, 20, &MaxValue); leftpoint = bi_side_search_float(buffer_float_data, point_notclear, 0 , ratio, 5, MaxValue*4); rightpoint = bi_side_search_float(buffer_float_data, point_notclear, 1 , ratio, 5, MaxValue*4); mylocation = zhixin_upward(buffer_float_data, leftpoint, rightpoint, ratio ,MaxValue); kalman_result = kalman_realtime(mylocation, &kalman_preData, &kalman_p); kalman_loop_num++; //kalman_result1 = kalman_realtime(kalman_result, &kalman_preData1, &kalman_p1); //kalman_result2 = kalman_realtime(kalman_result1, &kalman_preData2, &kalman_p2); //mylocation = 0.235; //sprintf(show_str, "location = %f\t\t",kalman_result2); //str2com(show_str); // Set_Zeros(buffer_int_data,745,865); // memset(buffer_int_data,0,sizeof(uint16_t) * 900); } // frcnt++; if(frcnt%2000 ==0) { uint16_t r0= fpga_read_reg(UPP_CNT); sprintf(show_str, " A %d %d %d ",frcnt,r0,cc); str2com(show_str); } break; } cc++; if(cc>80000) { uint16_t r0= fpga_read_reg(UPP_CNT); sprintf(show_str, "B %d %d %d ",calc_cnt,r0,cc); str2com(show_str); break; } } //str2com(show_str); continue; // SW_BREAKPOINT ; // printf("end of ccd \n"); // printf("over windows %d %d %d %d \n",light[24],light[25],light[2028],light[2029]); } }
static void sdk7786_pcie_clk_disable(struct clk *clk) { fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR); }
/* * FPGA-driven PCIe clocks * * Historically these include the oscillator, clock B (slots 2/3/4) and * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove * everything under a single PCIe clocks enable bit that happens to map * to the same bit position as the oscillator bit for earlier FPGA * versions. * * Given that the legacy clocks have the side-effect of shutting the CPU * off through the FPGA along with the PCI slots, we simply leave them in * their initial state and don't bother registering them with the clock * framework. */ static int sdk7786_pcie_clk_enable(struct clk *clk) { fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR); return 0; }
static int sdk7786_mode_pins(void) { return fpga_read_reg(MODSWR); }
uint16_t fpga_read_test(int file_desc) { return fpga_read_reg(file_desc, FPGA_REG_TEST); }