uint32_t fpga_upp_test(void) { // ADC_CFG 设置为4.是连续采集, 设置为0是按照帧数采集(参照下面采集帧数) fpga_write_reg(ADC_CFG,0x4); /// RUN_FR_CNT1 采集帧数, fpga_write_reg(RUN_FR_CNT1,0x1); fpga_write_reg(RUN_FR_CNT2,0x0); /// SELECT_CCD ==0 冰松的S12443_CCD SELECT_CCD ==1 东芝的 TCD1254GFG fpga_write_reg(SELECT_CCD,0x0); //CCD_TINT 积分时间 S12443_CCD ,设置范围50-5000 .积分实际单位为0.11us . 东芝的 TCD1254GFG 设置范围为1-128 积分实际单位为10us. fpga_write_reg(CCD_TINT,100); //// uppp 的fifo 读取点。 设置范围100-1000 . S12443_CCD :参考值 1000, TCD1254GFG :参考值 1000 fpga_write_reg(FIFO_RD_ST,2000); /// CCD_ST 采集开始。 fpga_write_reg(CCD_ST,0); dsp_delay(100); fpga_write_reg(CCD_ST,1); return 0; }
static int __init sdk7786_pci_init(void) { u16 data = fpga_read_reg(PCIECR); /* * Enable slot #4 if it's been specified on the command line. * * Optionally reroute if slot #4 has a card present while slot #3 * does not, regardless of command line value. * * Card presence is logically inverted. */ slot4en ?: (!(data & PCIECR_PRST4) && (data & PCIECR_PRST3)); if (slot4en) { pr_info("Activating PCIe slot#4 (disabling slot#3)\n"); data &= ~PCIECR_PCIEMUX1; fpga_write_reg(data, PCIECR); /* Warn about forced rerouting if slot#3 is occupied */ if ((data & PCIECR_PRST3) == 0) { pr_warning("Unreachable card detected in slot#3\n"); return -EBUSY; } } else pr_info("PCIe slot#4 disabled\n"); return 0; }
static void sdk7786_power_off(void) { fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR); /* * It can take up to 20us for the R8C to do its job, back off and * wait a bit until we've been shut off. Even though newer FPGA * versions don't set the ACK bit, the latency issue remains. */ while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0) cpu_sleep(); }
static int sdk7786_i2c_setup(void) { unsigned int tmp; /* * Hand over I2C control to the FPGA. */ tmp = fpga_read_reg(SBCR); tmp &= ~SCBR_I2CCEN; tmp |= SCBR_I2CMEN; fpga_write_reg(tmp, SBCR); return i2c_register_board_info(0, sdk7786_i2c_devices, ARRAY_SIZE(sdk7786_i2c_devices)); }
static void write_fpga_master_ctrl (void) { unsigned char v = 0; if (g_tx_enable) v |= bmFR_MC_ENABLE_TX; if (g_rx_enable) v |= bmFR_MC_ENABLE_RX; if (g_tx_reset) v |= bmFR_MC_RESET_TX; if (g_rx_reset) v |= bmFR_MC_RESET_RX; regval[3] = v; fpga_write_reg (FR_MASTER_CTRL, regval); }
void main_loop() { if (first) { first = FALSE; printf("main_loop CPUCS = 0x%x\r\n", CPUCS); } /* check for ep1 out data */ if(!(EP1OUTCS & bmEPBUSY)) { BYTE *buf_out = EP1OUTBUF; BYTE *buf_in = EP1INBUF; BYTE len_out = EP1OUTBC; BYTE len_in = 0; BOOL ok = FALSE; //printf("ep1 out\r\n"); /* decrypt data */ ep1_decrypt(buf_out, buf_out, len_out); /* handle command */ //if (buf_out[0] != CMD_FPGA_UPLOAD_DATA) // printf("cmd 0x%x len %d\r\n", buf_out[0], len_out); switch (buf_out[0]) { case CMD_WRITE_EEPROM: if (len_out > 5 && buf_out[1] == 0x42 && buf_out[2] == 0x55 && (buf_out[4] + 5) == len_out && eeprom_write(I2C_EEPROM_ADDRESS, buf_out[3], buf_out[4], buf_out + 5)) { ok = TRUE; } break; case CMD_READ_EEPROM: if (len_out == 5 && buf_out[1] == 0x33 && buf_out[2] == 0x81) { /* wait for ep1in ready */ while (EP1INCS & bmEPBUSY); if (eeprom_read(I2C_EEPROM_ADDRESS, buf_out[3], buf_out[4], buf_in)) { len_in = buf_out[4]; ok = TRUE; } } break; case CMD_WRITE_LED_TABLE: if (len_out > 3 && (buf_out[2] + 3) == len_out && buf_out[1] < sizeof (led_table)) { BYTE *dst = led_table + buf_out[1]; BYTE *src = buf_out + 3; BYTE len = buf_out[2]; while (len-- > 0) { *dst++ = *src++; if (dst == led_table + sizeof (led_table)) dst = led_table; } ok = TRUE; } break; case CMD_SET_LED_MODE: if (len_out == 6) { led_run = buf_out[1]; RCAP2L = buf_out[2]; RCAP2H = buf_out[3]; led_div = buf_out[4]; led_repeat = buf_out[5]; ok = TRUE; } break; case CMD_FPGA_UPLOAD_INIT: ok = fpga_upload_init(); break; case CMD_FPGA_UPLOAD_DATA: if (len_out > 2 && (buf_out[1] + 2) == len_out) { ok = fpga_upload_data(buf_out + 2, buf_out[1]); } break; case CMD_FPGA_WRITE_REGISTER: if (len_out > 2 && (2*buf_out[1] + 2) == len_out) { BYTE i; for (i = 0; i < buf_out[1]; i++) fpga_write_reg(buf_out[2 + 2*i], buf_out[2 + 2*i + 1]); ok = TRUE; } break; case CMD_FPGA_READ_REGISTER: if (len_out > 2 && (buf_out[1] + 2) == len_out) { BYTE i; /* wait for ep1in ready */ while (EP1INCS & bmEPBUSY); for (i = 0; i < buf_out[1]; i++) buf_in[i] = fpga_read_reg(buf_out[2 + i]); len_in = buf_out[1]; ok = TRUE; } break; case CMD_START_ACQUISITION: if (len_out == 1) { gpif_stuff_start(); ok = TRUE; } break; case CMD_ABORT_ACQUISITION_ASYNC: if (len_out == 1) { gpif_stuff_abort(); ok = TRUE; } break; case CMD_ABORT_ACQUISITION_SYNC: if (len_out == 2) { gpif_stuff_abort(); /* wait for ep1in ready */ while (EP1INCS & bmEPBUSY); buf_in[0] = buf_out[1] ^ 0xff; len_in = 1; ok = TRUE; } break; // CMD_RETURN_TO_BOOTLOADER 0x7c // CMD_GET_REVID 0x82 } if (!ok) { /* stall ep1 */ EP1OUTCS |= bmEPSTALL; /* FIXME: dont stall? */ printf("STALL\r\n"); } else if (len_in > 0) { /* send reply */ ep1_encrypt(buf_in, buf_in, len_in); SYNCDELAY; EP1INBC = len_in; } /* prepare ep1 out for next packet */ EP1OUTBC = 0xff; SYNCDELAY; } /* led stuff */ if (TF2) { static BYTE count = 0, index = 0; CLEAR_TIMER2(); if (led_run) { if (count == 0) { count = led_div; if (index < sizeof (led_table)) fpga_write_reg(5, led_table[index++]); if (index == sizeof (led_table) && led_repeat) index = 0; } else { count -= 1; } } } }
static void sdk7786_restart(char *cmd) { fpga_write_reg(0xa5a5, SRSTR); }
static void sdk7786_pcie_clk_disable(struct clk *clk) { fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR); }
/* * FPGA-driven PCIe clocks * * Historically these include the oscillator, clock B (slots 2/3/4) and * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove * everything under a single PCIe clocks enable bit that happens to map * to the same bit position as the oscillator bit for earlier FPGA * versions. * * Given that the legacy clocks have the side-effect of shutting the CPU * off through the FPGA along with the PCI slots, we simply leave them in * their initial state and don't bother registering them with the clock * framework. */ static int sdk7786_pcie_clk_enable(struct clk *clk) { fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR); return 0; }