int fsl_initdram(void) { phys_size_t dram_size; #ifdef CONFIG_SYS_DDR_RAW_TIMING #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....\n"); dram_size = fsl_ddr_sdram(); #else dram_size = fsl_ddr_sdram_size(); #endif #else #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initialzing DDR using fixed setting\n"); dram_size = fixed_sdram(); #else gd->ram_size = 0x80000000; return 0; #endif #endif erratum_a008850_post(); #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); #endif gd->ram_size = dram_size; return 0; }
phys_size_t initdram(int board_type) { phys_size_t dram_size; #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....\n"); dram_size = fsl_ddr_sdram(); #else dram_size = fsl_ddr_sdram_size(); #endif #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); #endif return dram_size; }