int x86_fsp_init(void)
{
	void *nvs;

	if (!gd->arch.hob_list) {
#ifdef CONFIG_ENABLE_MRC_CACHE
		nvs = fsp_prepare_mrc_cache();
#else
		nvs = NULL;
#endif
		/*
		 * The first time we enter here, call fsp_init().
		 * Note the execution does not return to this function,
		 * instead it jumps to fsp_continue().
		 */
		fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, BOOT_FULL_CONFIG, nvs);
	} else {
		/*
		 * The second time we enter here, adjust the size of malloc()
		 * pool before relocation. Given gd->malloc_base was adjusted
		 * after the call to board_init_f_mem() in arch/x86/cpu/start.S,
		 * we should fix up gd->malloc_limit here.
		 */
		gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
	}

	return 0;
}
Esempio n. 2
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int x86_fsp_init(void)
{
	if (!gd->arch.hob_list)
		fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, BOOT_FULL_CONFIG, NULL);

	return 0;
}
Esempio n. 3
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int arch_fsp_init(void)
{
	void *nvs;
	int stack = CONFIG_FSP_TEMP_RAM_ADDR;
	int boot_mode = BOOT_FULL_CONFIG;
#ifdef CONFIG_HAVE_ACPI_RESUME
	int prev_sleep_state = chipset_prev_sleep_state();
	gd->arch.prev_sleep_state = prev_sleep_state;
#endif

	if (!gd->arch.hob_list) {
#ifdef CONFIG_ENABLE_MRC_CACHE
		nvs = fsp_prepare_mrc_cache();
#else
		nvs = NULL;
#endif

#ifdef CONFIG_HAVE_ACPI_RESUME
		if (prev_sleep_state == ACPI_S3) {
			if (nvs == NULL) {
				/* If waking from S3 and no cache then */
				debug("No MRC cache found in S3 resume path\n");
				post_code(POST_RESUME_FAILURE);
				/* Clear Sleep Type */
				chipset_clear_sleep_state();
				/* Reboot */
				debug("Rebooting..\n");
				outb(SYS_RST | RST_CPU, IO_PORT_RESET);
				/* Should not reach here.. */
				panic("Reboot System");
			}

			/*
			 * DM is not avaiable yet at this point, hence call
			 * CMOS access library which does not depend on DM.
			 */
			stack = cmos_read32(CMOS_FSP_STACK_ADDR);
			boot_mode = BOOT_ON_S3_RESUME;
		}
#endif
		/*
		 * The first time we enter here, call fsp_init().
		 * Note the execution does not return to this function,
		 * instead it jumps to fsp_continue().
		 */
		fsp_init(stack, boot_mode, nvs);
	} else {
		/*
		 * The second time we enter here, adjust the size of malloc()
		 * pool before relocation. Given gd->malloc_base was adjusted
		 * after the call to board_init_f_init_reserve() in arch/x86/
		 * cpu/start.S, we should fix up gd->malloc_limit here.
		 */
		gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
	}

	return 0;
}
Esempio n. 4
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void ibm_fsp_init(void)
{
	/* Early initializations of the FSP interface */
	fsp_init();
	map_debug_areas();
	fsp_sysparam_init();

	/* Get ready to receive E0 class messages. We need to respond
	 * to some of these for the init sequence to make forward progress
	 */
	fsp_console_preinit();

	/* Get ready to receive OCC related messages */
	occ_fsp_init();

	/* Get ready to receive Memory [Un]corretable Error messages. */
	fsp_memory_err_init();

	/* Initialize elog access */
	fsp_elog_read_init();
	fsp_elog_write_init();

	/* Initiate dump service */
	fsp_dump_init();

	/* Start FSP/HV state controller & perform OPL */
	fsp_opl();

	/* Preload hostservices lids */
	hservices_lid_preload();

	/* Initialize SP attention area */
	fsp_attn_init();

	/* Initialize monitoring of TOD topology change event notification */
	fsp_chiptod_init();

	/* Send MDST table notification to FSP */
	op_display(OP_LOG, OP_MOD_INIT, 0x0000);
	fsp_mdst_table_init();

	/* Initialize the panel */
	op_display(OP_LOG, OP_MOD_INIT, 0x0001);
	fsp_oppanel_init();

	/* Start the surveillance process */
	op_display(OP_LOG, OP_MOD_INIT, 0x0002);
	fsp_init_surveillance();

	/* IPMI */
	fsp_ipmi_init();
	ipmi_opal_init();

	/* Initialize sensor access */
	op_display(OP_LOG, OP_MOD_INIT, 0x0003);
	fsp_init_sensor();

	/* LED */
	op_display(OP_LOG, OP_MOD_INIT, 0x0004);
	fsp_led_init();

	/* Monitor for DIAG events */
	op_display(OP_LOG, OP_MOD_INIT, 0x0005);
	fsp_init_diag();

	/* Finish initializing the console */
	op_display(OP_LOG, OP_MOD_INIT, 0x0006);
	fsp_console_init();

	/* Read our initial RTC value */
	op_display(OP_LOG, OP_MOD_INIT, 0x0008);
	fsp_rtc_init();

	/* Initialize code update access */
	op_display(OP_LOG, OP_MOD_INIT, 0x0009);
	fsp_code_update_init();

	/* EPOW */
	op_display(OP_LOG, OP_MOD_INIT, 0x000A);
	fsp_epow_init();

	/* EPOW */
	op_display(OP_LOG, OP_MOD_INIT, 0x000B);
	fsp_dpo_init();

	/* Setup console */
	if (fsp_present())
		fsp_console_add_nodes();

	if (proc_gen >= proc_gen_p9)
		prd_init();
}