static int _spu_dma_transfer(void *from, uint32 dest, uint32 length, int block,
g2_dma_callback_t callback, ptr_t cbdata)
{
/* Adjust destination to SPU RAM */
dest += 0x00800000;
return g2_dma_transfer(from, (void *) dest, length, block, callback, cbdata, 0,
SPU_DMA_MODE, 1, 1);
}
static void spu_cb(void * p)
{
if (p) {
dma_chain_t * chain = (dma_chain_t *) p;
if (chain->src == NULL) {
free_chain(chain);
} else {
sem_signal(chain->sema);
if (chain->waiting_thd)
thd_schedule_next(chain->waiting_thd);
chain->dest = 0; /* mark dma completed */
}
if (spu_chain_head == NULL)
;//draw_unlock();
vid_border_color(0, 0, 0);
spu_transfering = 0;
} else
;//bba_lock();
//asic_evt_disable(ASIC_EVT_EXP_PCI, ASIC_IRQB);
if (spu_chain_head) {
dma_chain_t * chain = spu_chain_head;
spu_transfering = 1;
vid_border_color(0, 255, 0);
switch(chain->type) {
/* case DMA_TYPE_VRAM: */
/* pvr_txr_load_dma(chain->src, chain->dest, */
/* chain->count, 0, spu_cb, chain); */
/* break; */
case DMA_TYPE_SPU:
dma_cache_flush(chain->src, chain->count);
spu_dma_transfer(chain->src, chain->dest, chain->count, 0,
spu_cb, chain);
break;
case DMA_TYPE_BBA_RX:
g2_dma_transfer(chain->dest, chain->src, chain->count, 0,
spu_cb, chain, 1, bba_dma_mode, 1, 3);
break;
default:
panic("got bad dma chain type in spu_cb\n");
}
spu_chain_head = chain->next;
} else {
//asic_evt_enable(ASIC_EVT_EXP_PCI, ASIC_IRQB);
;//bba_unlock();
}
}
MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
{
reg &= 0xFFF;
if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
return; /* disabled */
}
switch( reg ) {
case IDEALTSTATUS: /* Device control */
ide_write_control( val );
break;
case IDEDATA:
ide_write_data_pio( val );
break;
case IDEFEAT:
if( ide_can_write_regs() )
idereg.feature = (uint8_t)val;
break;
case IDECOUNT:
if( ide_can_write_regs() )
idereg.count = (uint8_t)val;
break;
case IDELBA0:
if( ide_can_write_regs() )
idereg.lba0 = (uint8_t)val;
break;
case IDELBA1:
if( ide_can_write_regs() )
idereg.lba1 = (uint8_t)val;
break;
case IDELBA2:
if( ide_can_write_regs() )
idereg.lba2 = (uint8_t)val;
break;
case IDEDEV:
if( ide_can_write_regs() )
idereg.device = (uint8_t)val;
break;
case IDECMD:
if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
ide_write_command( (uint8_t)val );
}
break;
case IDEDMASH4:
MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );
break;
case IDEDMASIZ:
MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
break;
case IDEDMADIR:
MMIO_WRITE( EXTDMA, reg, val & 1 );
break;
case IDEDMACTL1:
case IDEDMACTL2:
MMIO_WRITE( EXTDMA, reg, val & 0x01 );
asic_ide_dma_transfer( );
break;
case IDEACTIVATE:
if( val == 0x001FFFFF ) {
idereg.interface_enabled = TRUE;
/* Conventional wisdom says that this is necessary but not
* sufficient to enable the IDE interface.
*/
} else if( val == 0x000042FE ) {
idereg.interface_enabled = FALSE;
}
break;
case G2DMA0EXT: case G2DMA0SH4: case G2DMA0SIZ:
case G2DMA1EXT: case G2DMA1SH4: case G2DMA1SIZ:
case G2DMA2EXT: case G2DMA2SH4: case G2DMA2SIZ:
case G2DMA3EXT: case G2DMA3SH4: case G2DMA3SIZ:
MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );
break;
case G2DMA0MOD: case G2DMA1MOD: case G2DMA2MOD: case G2DMA3MOD:
MMIO_WRITE( EXTDMA, reg, val & 0x07 );
break;
case G2DMA0DIR: case G2DMA1DIR: case G2DMA2DIR: case G2DMA3DIR:
MMIO_WRITE( EXTDMA, reg, val & 0x01 );
break;
case G2DMA0CTL1:
case G2DMA0CTL2:
MMIO_WRITE( EXTDMA, reg, val & 1);
g2_dma_transfer( 0 );
break;
case G2DMA0STOP:
MMIO_WRITE( EXTDMA, reg, val & 0x37 );
break;
case G2DMA1CTL1:
case G2DMA1CTL2:
MMIO_WRITE( EXTDMA, reg, val & 1);
g2_dma_transfer( 1 );
break;
case G2DMA1STOP:
MMIO_WRITE( EXTDMA, reg, val & 0x37 );
break;
case G2DMA2CTL1:
case G2DMA2CTL2:
MMIO_WRITE( EXTDMA, reg, val &1 );
g2_dma_transfer( 2 );
break;
case G2DMA2STOP:
MMIO_WRITE( EXTDMA, reg, val & 0x37 );
break;
case G2DMA3CTL1:
case G2DMA3CTL2:
MMIO_WRITE( EXTDMA, reg, val &1 );
g2_dma_transfer( 3 );
break;
case G2DMA3STOP:
MMIO_WRITE( EXTDMA, reg, val & 0x37 );
break;
case PVRDMA2CTL1:
case PVRDMA2CTL2:
MMIO_WRITE( EXTDMA, reg, val & 1 );
pvr_dma2_transfer();
break;
default:
MMIO_WRITE( EXTDMA, reg, val );
}
}