/** * sbLatePost - Prepare Southbridge to boot to OS. * * * * @param[in] pConfig Southbridge configuration structure pointer. * */ VOID sbLatePost ( IN AMDSBCFG* pConfig ) { // UINT16 dwVar; BUILDPARAM *pStaticOptions; pStaticOptions = &(pConfig->BuildParameters); commonInitLateBoot (pConfig); sataInitLatePost (pConfig); gecInitLatePost (pConfig); hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit #ifndef NO_EC_SUPPORT ecInitLatePost (pConfig); #endif sbPcieGppLateInit (pConfig); }
/** * sbLatePost - Prepare Southbridge to boot to OS. * * * * @param[in] pConfig Southbridge configuration structure pointer. * */ VOID sbLatePost ( IN AMDSBCFG* pConfig ) { // UINT16 dwVar; BUILDPARAM *pStaticOptions; pStaticOptions = &(pConfig->BuildParameters); TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n")); commonInitLateBoot (pConfig); sataInitLatePost (pConfig); gecInitLatePost (pConfig); hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit #ifndef NO_EC_SUPPORT ecInitLatePost (pConfig); #endif sbPcieGppLateInit (pConfig); hwmImcInit (pConfig); // hwmSbtsiAutoPollingOff (pConfig); imcDisarmSurebootTimer (pConfig); usbInitLate (pConfig); // Init USB StressResetModeLate (pConfig); // }
static void gec_init(struct device *dev) { gecInitAfterPciEnum(sb_config); gecInitLatePost(sb_config); printk(BIOS_DEBUG, "gec hda enabled\n"); }