int main()
{
colossal::job_generator gen1(
0.002616272, 5.009914, 2.174681, 3.394791,
2.532164, 4.070759, 6.570099, 0.9067149, 1.843567);
gen1.seed(time(NULL));
colossal::job_generator gen2(
0.004299325, 2.562229, 1.038189, 2.600581,
1.716938, 4.388895, 5.534811, 1.609197, 1.604422);
gen2.seed(time(NULL) + 1);
colossal::job j1 = gen1();
colossal::job j2 = gen2();
colossal::job_tracker jt(10000, 6000);
colossal::pool &mod = jt.add_pool("modeling", 1000, 1000, 1, 500, 5000, colossal::pool::SCHED_FAIR);
colossal::pool &prod = jt.add_pool("prod", 1000, 1000, 1, 500, 5000, colossal::pool::SCHED_FAIR);
mod.add_job(j1);
prod.add_job(j2);
jt.scale_minshares();
jt.process();
printf("------------ WORKLOAD ------------\n");
printf("%s\n", mod.to_str().c_str());
printf("%s\n", prod.to_str().c_str());
printf("----------------------------------\n");
return 0;
}
int main(int argc, char *argv[])
{
#ifdef FAIL
int *g = gen1();
#else
generator_t(int) g = gen1();
#endif
printf("%d", *generator_next(g));
exit(0);
}
int main()
{
M6502 *mpu = M6502_new(0, 0, 0); /* Make a 6502 */
unsigned pc = 0x1000; /* PC for 'assembly' */
/* Install the two callback functions defined above.
*/
M6502_setCallback(mpu, call, WRCH, wrch); /* Calling FFEE -> wrch() */
M6502_setCallback(mpu, call, 0, done); /* Calling 0 -> done() */
/* A few macros that dump bytes into the 6502's memory.
*/
# define gen1(X) (mpu->memory[pc++]= (uint8_t)(X))
# define gen2(X,Y) gen1(X); gen1(Y)
# define gen3(X,Y,Z) gen1(X); gen2(Y,Z)
/* Hand-assemble the program.
*/
gen2(0xA2, 'A' ); // LDX #'A'
gen1(0x8A ); // TXA
gen3(0x20,0xEE,0xFF); // JSR FFEE
gen1(0xE8 ); // INX
gen2(0xE0, 'Z'+1 ); // CPX #'Z'+1
gen2(0xD0, -9 ); // BNE 0x1002
gen2(0xA9, '\n' ); // LDA #'\n'
gen3(0x20,0xEE,0xFF); // JSR FFEE
gen2(0x00,0x00 ); // BRK
/* Just for fun: disssemble the program.
*/
{
char insn[64];
uint16_t ip= 0x1000;
while (ip < pc)
{
ip += M6502_disassemble(mpu, ip, insn);
printf("%04X %s\n", ip, insn);
}
}
/* Point the RESET vector at the first instruction in the assembled
* program.
*/
M6502_setVector(mpu, RST, 0x1000);
/* Reset the 6502 and run the program.
*/
M6502_reset(mpu);
M6502_run(mpu);
M6502_delete(mpu); /* We never reach here, but what the hey. */
return 0;
}
int main()
{
Tempo::job_generator gen(0.01, 5000, 2000, 80, 80, 0.7, 3000, 300, 300);
gen.seed(time(NULL));
Tempo::job j1 = gen();
printf("%s\n", j1.to_str().c_str());
Tempo::job_generator gen1(0.1, 20, 20, 80, 0.7, 0.7, 20, 100, 20);
gen1.seed(time(NULL) + 1);
Tempo::job j2 = gen1();
Tempo::job j3 = gen1();
printf("\n%s\n\n%s\n", j2.to_str().c_str(), j3.to_str().c_str());
return 0;
}
int main(int argc, char *argv[])
{
M6502 *mpu = M6502_new(0, 0, 0);
parse_args(argc, argv, mpu);
unsigned pc = 0x1000;
unsigned saved_pc;
M6502_setCallback(mpu, call, 0, done );
M6502_setCallback(mpu, call, 0xffee, oswrch);
gen2(0xa2, 0xff ); // LDX #&FF
gen1(0x9a ); // TXS
gen2(0xa9, 'A' ); // LDA #'A'
// LDA #'B' is 0xa9, 0x42. So if we execute a JSR at 0x42a7, it will
// push 0x42 and then 0xa9 onto the stack. Since the stack grows downwards
// those bytes will be in the right order for execution.
gen3(0x4c, 0xa7, 0x42); // JMP &42A7
pc = 0x42a7;
gen3(0x20, 0x00, 0x30); // JSR &3000
saved_pc = pc;
pc = 0x3000;
gen3(0x4c, 0xfe, 0x01); // JMP &01FE
pc = 0x200;
gen3(0x20, 0xee, 0xff); // JSR &FFEE
gen1(0x60 ); // RTS
pc = saved_pc;
// Let's do the same thing again, but this time code has already been
// executed from that address on the stack, so we're verifying the change
// is picked up. We do LDA #'C' this time, so we execute the JSR from
// 0x43a7.
gen3(0x4c, 0xa7, 0x43); // JMP &43A7
pc = 0x43a7;
gen3(0x20, 0x00, 0x30); // JSR &3000
gen2(0x00, 0x00 ); // BRK
M6502_setVector(mpu, RST, 0x1000);
M6502_reset(mpu);
M6502_run(mpu);
M6502_delete(mpu); /* We never reach here, but what the hey. */
return 0;
}
//=======================================================================================================
void random_sample() {
util::random::mt19937 gen1;
gen1.init_seed(123);
std::cout << "Random - mt19937: " << gen1.random() << std::endl;
std::cout << "Random - mt19937: " << gen1() << std::endl;
std::cout << "Random - mt19937 - between [100, 10000): " << gen1.random_between(100, 10000) << std::endl;
}
int main() {
srand((unsigned)time(NULL));
for (int i = 1; i <= 4; ++i) gen1(i);
for (int i = 5; i <= 8; ++i) gen2(i);
for (int i = 9; i <= 12; ++i) gen3(i);
for (int i = 13; i <= 16; ++i) gen4(i);
for (int i = 17; i <= 20; ++i) gen5(i);
return 0;
}
int main(int argc, char *argv[])
{
M6502 *mpu = M6502_new(0, 0, 0);
parse_args(argc, argv, mpu);
unsigned pc = 0x1000;
M6502_setCallback(mpu, call, 0, done);
M6502_setCallback(mpu, call, 0xffee, oswrch);
M6502_setCallback(mpu, write, 0x42, wr );
gen2(0xa9, '>' ); // LDA #'>'
gen3(0x20, 0xee, 0xff); // JSR &FFEE
gen2(0xa2, 'A' ); // LDX #'A'
gen3(0x8e, 0x42, 0x00); // STX &0042
gen3(0x20, 0x00, 0x60); // JSR &6000
gen1(0xe8 ); // INX
gen2(0xe0, 'Z'+1 ); // CPX #('Z'+1)
gen2(0x90, 0xf5 ); // BCC to STX
gen2(0xa0, 0x05 ); // LDY #&05
gen2(0xa9, '>' ); // LDA #'>'
gen3(0x20, 0xee, 0xff); // JSR &FFEE
gen2(0xa2, 'A' ); // LDX #'A'
gen2(0x96, 0x42-0x05 ); // STX (&42-&05),Y
gen3(0x20, 0x00, 0x60); // JSR &6000
gen1(0xe8 ); // INX
gen2(0xe0, 'Z'+1 ); // CPX #('Z'+1)
gen2(0x90, 0xf6 ); // BCC to STX
gen2(0x00, 0x00 ); // BRK
pc = 0x2000;
gen3(0x20, 0xee, 0xff); // JSR &FFEE
gen1(0x60 ); // RTS
M6502_setVector(mpu, RST, 0x1000);
M6502_reset(mpu);
M6502_run(mpu);
M6502_delete(mpu); /* We never reach here, but what the hey. */
return 0;
}
//=======================================================================================================
void random_sample() {
printf("\n");
printf("===============begin random sample==============\n");
util::random::mt19937 gen1;
gen1.init_seed(123);
printf("Random - mt19937: %u\n", gen1.random());
printf("Random - mt19937: %u\n", gen1());
printf("Random - mt19937 - between [100, 10000): %d\n", gen1.random_between(100, 10000));
printf("===============end random sample==============\n");
}
code *nteh_unwind(regm_t retregs,unsigned index)
{ code *c;
code cs;
code *cs1;
code *cs2;
regm_t desregs;
int reg;
int local_unwind;
// Shouldn't this always be CX?
#if SCPP
reg = AX;
#else
reg = CX;
#endif
#if MARS
local_unwind = RTLSYM_D_LOCAL_UNWIND2;
#else
local_unwind = RTLSYM_LOCAL_UNWIND2;
#endif
desregs = (~rtlsym[local_unwind]->Sregsaved & (ALLREGS)) | mask[reg];
gensaverestore(retregs & desregs,&cs1,&cs2);
c = getregs(desregs);
cs.Iop = 0x8D;
cs.Irm = modregrm(2,reg,BPRM);
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL1 = FLconst;
// EBP offset of __context.prev
cs.IEV1.Vint = nteh_EBPoffset_prev();
c = gen(c,&cs); // LEA ECX,contextsym
genc2(c,0x68,0,index); // PUSH index
gen1(c,0x50 + reg); // PUSH ECX
#if MARS
//gencs(c,0xB8+AX,0,FLextern,nteh_scopetable()); // MOV EAX,&scope_table
gencs(c,0x68,0,FLextern,nteh_scopetable()); // PUSH &scope_table
gencs(c,0xE8,0,FLfunc,rtlsym[local_unwind]); // CALL __d_local_unwind2()
genc2(c,0x81,modregrm(3,0,SP),12); // ADD ESP,12
#else
gencs(c,0xE8,0,FLfunc,rtlsym[local_unwind]); // CALL __local_unwind2()
genc2(c,0x81,modregrm(3,0,SP),8); // ADD ESP,8
#endif
c = cat4(cs1,c,cs2,NULL);
return c;
}
int main()
{
Tempo::job_generator gen1(0.01, 3, 3, 1, 1, 0.6, 0.6, 0.2, 0.2);
gen1.seed(time(NULL));
Tempo::job j1 = gen1();
Tempo::job j2 = gen1();
Tempo::job_tracker jt(1, 1);
Tempo::pool &mod = jt.add_pool("modeling", 10, 10, 1, 1, 1, Tempo::pool::SCHED_FAIR);
mod.add_job(j1);
mod.add_job(j2);
jt.process();
printf("------------ WORKLOAD ------------\n");
printf("%s\n", mod.to_str().c_str());
printf("----------------------------------\n");
return 0;
}
const StructLayoutInfo &typeLayout(SgType *t)
{
t = t->stripTypedefsAndModifiers();
TypeLayoutAttribute *tla;
if (t->attributeExists("TypeLayout"))
{
tla = static_cast<TypeLayoutAttribute *>(t->getAttribute("TypeLayout"));
}
else
{
SystemPrimitiveTypeLayoutGenerator gen1(NULL);
NonpackedTypeLayoutGenerator gen(&gen1);
tla = new TypeLayoutAttribute(gen.layoutType(t));
t->addNewAttribute("TypeLayout", tla);
}
return tla->info;
}
void pgsTestSuite::test_generator_string(void)
{
const int nb_iterations = 100;
// Generate empty strings because of inconsistent arguments
{
pgsStringGen gen1(0, 0, 10);
pgsStringGen gen2(10, 20, 0);
// pgsStringGen gen3(-10, -20, 10);
// pgsStringGen gen4(10, 20, -10);
TS_ASSERT(gen1.random() == wxT(""));
TS_ASSERT(gen2.random() == wxT(""));
// TS_ASSERT(gen3.random() == wxT(""));
// TS_ASSERT(gen4.random() == wxT(""));
}
// Generate strings with 'a' only
{
pgsVectorChar chars;
chars.Add(wxT('a'));
chars.Add(wxT('a'));
pgsStringGen gen(2, 2, 3, wxDateTime::GetTimeNow(), chars);
for (int i = 0; i < nb_iterations; i++)
{
TS_ASSERT(gen.random() == wxT("aa aa aa"));
}
}
// Test strings that are in fact numbers
// Test the size of generated strings
{
pgsVectorChar chars;
chars.Add(wxT('1'));
chars.Add(wxT('2'));
chars.Add(wxT('3'));
chars.Add(wxT('4'));
pgsStringGen gen(5, 5, 1, wxDateTime::GetTimeNow(), chars);
wxString result;
for (int i = 0; i < nb_iterations; i++)
{
result = gen.random();
long aux_res;
result.ToLong(&aux_res);
TS_ASSERT(MAPM(result.mb_str()) == aux_res && result.Length() == 5);
}
}
// Test the size of generated strings
{
pgsStringGen gen(10, 11, 3, 123);
pgsStringGen comparator(10, 11, 3, 123);
wxString result;
for (int i = 0; i < nb_iterations; i++)
{
result = gen.random();
TS_ASSERT(result == comparator.random());
TS_ASSERT(result.Length() >= 32 && result.Length() <= 35);
}
}
// Test copy constructor
{
// Create a generator and generate values
pgsStringGen gen(10, 11, 3, 123456789L);
wxString result, res_cmp;
for (int i = 0; i < nb_iterations / 2; i++)
{
result = gen.random();
}
// Copy this generator to a new one
// Both generators must generate the same values
pgsStringGen comparator(gen);
for (int i = nb_iterations / 2; i < nb_iterations; i++)
{
result = gen.random();
res_cmp = comparator.random();
TS_ASSERT(result == res_cmp);
}
}
// Test assignment operator
{
// Create two different generators and generate values
pgsStringGen gen(20, 30, 20);
pgsStringGen comparator(0, 0, 10);
wxString result, res_cmp;
for (int i = 0; i < nb_iterations / 2; i++)
{
result = gen.random();
res_cmp = comparator.random();
}
// Copy one of the generators to the other one
// Both generators must generate the same values
comparator = gen;
for (int i = nb_iterations / 2; i < nb_iterations; i++)
{
result = gen.random();
res_cmp = comparator.random();
TS_ASSERT(result == res_cmp);
}
}
}
code *nteh_monitor_prolog(Symbol *shandle)
{
/*
* PUSH handle
* PUSH offset _d_monitor_handler
* PUSH FS:__except_list
* MOV FS:__except_list,ESP
* CALL _d_monitor_prolog
*/
code *c1 = NULL;
code *c;
code cs;
Symbol *s;
regm_t desregs;
assert(config.flags2 & CFG2seh); // BUG: figure out how to implement for other EX's
if (shandle->Sclass == SCfastpar)
{ assert(shandle->Spreg != DX);
c = gen1(NULL,0x50 + shandle->Spreg); // PUSH shandle
}
else
{
// PUSH shandle
#if 0
c = genc1(NULL,0xFF,modregrm(2,6,4),FLconst,4 * (1 + needframe) + shandle->Soffset + localsize);
c->Isib = modregrm(0,4,SP);
#else
useregs(mCX);
c = genc1(NULL,0x8B,modregrm(2,CX,4),FLconst,4 * (1 + needframe) + shandle->Soffset + localsize);
c->Isib = modregrm(0,4,SP);
gen1(c,0x50 + CX); // PUSH ECX
#endif
}
s = rtlsym[RTLSYM_MONITOR_HANDLER];
c = gencs(c,0x68,0,FLextern,s); // PUSH offset _d_monitor_handler
makeitextern(s);
#if 0
cs.Iop = 0xFF;
cs.Irm = modregrm(0,6,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = rtlsym[RTLSYM_EXCEPT_LIST];
cs.IEVoffset1 = 0;
gen(c,&cs); // PUSH FS:__except_list
#else
useregs(mDX);
cs.Iop = 0x8B;
cs.Irm = modregrm(0,DX,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = rtlsym[RTLSYM_EXCEPT_LIST];
cs.IEVoffset1 = 0;
c1 = gen(c1,&cs); // MOV EDX,FS:__except_list
gen1(c,0x50 + DX); // PUSH EDX
#endif
s = rtlsym[RTLSYM_MONITOR_PROLOG];
desregs = ~s->Sregsaved & ALLREGS;
c = cat(c,getregs(desregs));
c = gencs(c,0xE8,0,FLfunc,s); // CALL _d_monitor_prolog
cs.Iop = 0x89;
NEWREG(cs.Irm,SP);
gen(c,&cs); // MOV FS:__except_list,ESP
return cat(c1,c);
}
code *nteh_prolog()
{
code cs;
code *c1;
code *c;
if (usednteh & NTEHpassthru)
{
/* An sindex value of -2 is a magic value that tells the
* stack unwinder to skip this frame.
*/
assert(config.exe & (EX_LINUX | EX_LINUX64 | EX_OSX | EX_OSX64 | EX_FREEBSD | EX_FREEBSD64 | EX_SOLARIS | EX_SOLARIS64));
cs.Iop = 0x68;
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vint = -2;
return gen(CNIL,&cs); // PUSH -2
}
/* Generate instance of struct __nt_context on stack frame:
[ ] // previous ebp already there
push -1 // sindex
mov EDX,FS:__except_list
push offset FLAT:scope_table // stable (not for MARS or C++)
push offset FLAT:__except_handler3 // handler
push EDX // prev
mov FS:__except_list,ESP
sub ESP,8 // info, esp for __except support
*/
// useregs(mAX); // What is this for?
cs.Iop = 0x68;
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vint = -1;
c1 = gen(CNIL,&cs); // PUSH -1
if (usednteh & NTEHcpp || MARS)
{
// PUSH &framehandler
cs.IFL2 = FLframehandler;
#if MARS
nteh_scopetable();
#endif
}
else
{
// Do stable
cs.Iflags |= CFoff;
cs.IFL2 = FLextern;
cs.IEVsym2 = nteh_scopetable();
cs.IEVoffset2 = 0;
c1 = gen(c1,&cs); // PUSH &scope_table
cs.IFL2 = FLextern;
cs.IEVsym2 = rtlsym[RTLSYM_EXCEPT_HANDLER3];
makeitextern(rtlsym[RTLSYM_EXCEPT_HANDLER3]);
}
c = gen(NULL,&cs); // PUSH &__except_handler3
if (config.exe == EX_NT)
{
makeitextern(rtlsym[RTLSYM_EXCEPT_LIST]);
#if 0
cs.Iop = 0xFF;
cs.Irm = modregrm(0,6,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = rtlsym[RTLSYM_EXCEPT_LIST];
cs.IEVoffset1 = 0;
gen(c,&cs); // PUSH FS:__except_list
#else
useregs(mDX);
cs.Iop = 0x8B;
cs.Irm = modregrm(0,DX,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = rtlsym[RTLSYM_EXCEPT_LIST];
cs.IEVoffset1 = 0;
gen(c1,&cs); // MOV EDX,FS:__except_list
gen1(c,0x50 + DX); // PUSH EDX
#endif
cs.Iop = 0x89;
NEWREG(cs.Irm,SP);
gen(c,&cs); // MOV FS:__except_list,ESP
}
c = genc2(c,0x81,modregrm(3,5,SP),8); // SUB ESP,8
return cat(c1,c);
}
int main(int argc, char *argv[])
{
M6502 *mpu = M6502_new(0, 0, 0);
parse_args(argc, argv, mpu);
unsigned pc = 0x1000;
unsigned saved_pc;
M6502_setCallback(mpu, call, 0xf000, done );
M6502_setCallback(mpu, call, 0xffee, oswrch);
gen2(0xa2, 0xff ); // LDX #&FF
gen1(0x9a ); // TXS
gen2(0xa9, 'A' ); // LDA #'A'
// LDA #'B' is 0xa9, 0x42. So if we execute a BRK at 0x42a7, it will
// push 0x42, 0xa9 and the flags onto the stack. Since the stack grows
// downwards those bytes will be in the right order for execution. We'll
// additionally push an LDX immediate opcode so we can "execute" the flags
// value. We can nearly force the flags to be whatever we like using PLP,
// although the BRK will set the B and X bits in the stacked value. We
// demonstrate this by explicitly masking off those bits in the values we
// force into the flags.
enum {
flagX= (1<<5), /* unused */
flagB= (1<<4) /* irq from brk */
};
uint8_t mask = ~(flagX | flagB);
gen2(0xa0, '0' & mask); // LDY #('0' with B/X masked off)
gen1(0x5a ); // PHY
gen1(0x28 ); // PLP
gen3(0x4c, 0xa7, 0x42); // JMP &42A7
pc = 0x42a7;
gen2(0x00, 0x00 ); // BRK
saved_pc = pc;
pc = 0x0; // BRK vector
gen2(0xa9, 0xa2 ); // LDA #<LDX # opcode>
gen1(0x48 ); // PHA
gen3(0x4c, 0xfc, 0x01); // JMP &01FC
pc = 0x200;
gen3(0x20, 0xee, 0xff); // JSR &FFEE
gen1(0x8a ); // TXA
gen3(0x20, 0xee, 0xff); // JSR &FFEE
gen1(0x68 ); // PLA
gen1(0x40 ); // RTI
pc = saved_pc;
// Let's do the same thing again, but this time code has already been
// executed from that address on the stack, so we're verifying the change
// is picked up. We do LDA #'C' this time, so we execute the BRK from
// 0x43a7.
gen2(0xa0, '1' & mask); // LDY #('1' with B/X masked off)
gen1(0x5a ); // PHY
gen1(0x28 ); // PLP
gen3(0x4c, 0xa7, 0x43); // JMP &43A7
pc = 0x43a7;
gen2(0x00, 0x00 ); // BRK
gen3(0x4c, 0x00, 0xf0); // JMP &F000 (quit)
M6502_setVector(mpu, RST, 0x1000);
M6502_reset(mpu);
M6502_run(mpu);
M6502_delete(mpu); /* We never reach here, but what the hey. */
return 0;
}
code *xmmeq(elem *e, unsigned op, elem *e1, elem *e2,regm_t *pretregs)
{
tym_t tymll;
unsigned reg;
int i;
code *cl,*cr,*c,cs;
elem *e11;
bool regvar; /* TRUE means evaluate into register variable */
regm_t varregm;
unsigned varreg;
targ_int postinc;
//printf("xmmeq(e1 = %p, e2 = %p, *pretregs = %s)\n", e1, e2, regm_str(*pretregs));
int e2oper = e2->Eoper;
tym_t tyml = tybasic(e1->Ety); /* type of lvalue */
regm_t retregs = *pretregs;
if (!(retregs & XMMREGS))
retregs = XMMREGS; // pick any XMM reg
cs.Iop = (op == OPeq) ? xmmstore(tyml) : op;
regvar = FALSE;
varregm = 0;
if (config.flags4 & CFG4optimized)
{
// Be careful of cases like (x = x+x+x). We cannot evaluate in
// x if x is in a register.
if (isregvar(e1,&varregm,&varreg) && // if lvalue is register variable
doinreg(e1->EV.sp.Vsym,e2) // and we can compute directly into it
)
{ regvar = TRUE;
retregs = varregm;
reg = varreg; /* evaluate directly in target register */
}
}
if (*pretregs & mPSW && !EOP(e1)) // if evaluating e1 couldn't change flags
{ // Be careful that this lines up with jmpopcode()
retregs |= mPSW;
*pretregs &= ~mPSW;
}
cr = scodelem(e2,&retregs,0,TRUE); // get rvalue
// Look for special case of (*p++ = ...), where p is a register variable
if (e1->Eoper == OPind &&
((e11 = e1->E1)->Eoper == OPpostinc || e11->Eoper == OPpostdec) &&
e11->E1->Eoper == OPvar &&
e11->E1->EV.sp.Vsym->Sfl == FLreg
)
{
postinc = e11->E2->EV.Vint;
if (e11->Eoper == OPpostdec)
postinc = -postinc;
cl = getlvalue(&cs,e11,RMstore | retregs);
freenode(e11->E2);
}
else
{ postinc = 0;
cl = getlvalue(&cs,e1,RMstore | retregs); // get lvalue (cl == CNIL if regvar)
}
c = getregs_imm(varregm);
reg = findreg(retregs & XMMREGS);
cs.Irm |= modregrm(0,(reg - XMM0) & 7,0);
if ((reg - XMM0) & 8)
cs.Irex |= REX_R;
// Do not generate mov from register onto itself
if (!(regvar && reg == XMM0 + ((cs.Irm & 7) | (cs.Irex & REX_B ? 8 : 0))))
c = gen(c,&cs); // MOV EA+offset,reg
if (e1->Ecount || // if lvalue is a CSE or
regvar) // rvalue can't be a CSE
{
c = cat(c,getregs_imm(retregs)); // necessary if both lvalue and
// rvalue are CSEs (since a reg
// can hold only one e at a time)
cssave(e1,retregs,EOP(e1)); // if lvalue is a CSE
}
c = cat4(cr,cl,c,fixresult(e,retregs,pretregs));
Lp:
if (postinc)
{
int reg = findreg(idxregm(&cs));
if (*pretregs & mPSW)
{ // Use LEA to avoid touching the flags
unsigned rm = cs.Irm & 7;
if (cs.Irex & REX_B)
rm |= 8;
c = genc1(c,0x8D,buildModregrm(2,reg,rm),FLconst,postinc);
if (tysize(e11->E1->Ety) == 8)
code_orrex(c, REX_W);
}
else if (I64)
{
c = genc2(c,0x81,modregrmx(3,0,reg),postinc);
if (tysize(e11->E1->Ety) == 8)
code_orrex(c, REX_W);
}
else
{
if (postinc == 1)
c = gen1(c,0x40 + reg); // INC reg
else if (postinc == -(targ_int)1)
c = gen1(c,0x48 + reg); // DEC reg
else
{
c = genc2(c,0x81,modregrm(3,0,reg),postinc);
}
}
}
freenode(e1);
return c;
}
Multab*
mulcon0(long v)
{
int a1, a2, g;
Multab *m, *m1;
char hint[10];
if(v < 0)
v = -v;
/*
* look in cache
*/
m = multab;
for(g=0; g<nelem(multab); g++) {
if(m->val == v) {
if(m->code[0] == 0)
return 0;
return m;
}
m++;
}
/*
* select a spot in cache to overwrite
*/
multabp++;
if(multabp < 0 || multabp >= nelem(multab))
multabp = 0;
m = multab+multabp;
m->val = v;
mulval = v;
/*
* look in execption hint table
*/
a1 = 0;
a2 = hintabsize;
for(;;) {
if(a1 >= a2)
goto no;
g = (a2 + a1)/2;
if(v < hintab[g].val) {
a2 = g;
continue;
}
if(v > hintab[g].val) {
a1 = g+1;
continue;
}
break;
}
if(docode(hintab[g].hint, m->code, 1, 0))
return m;
print("multiply table failure %ld\n", v);
m->code[0] = 0;
return 0;
no:
/*
* try to search
*/
hint[0] = 0;
for(g=1; g<=6; g++) {
if(g >= 6 && v >= 65535)
break;
mulcp = hint+g;
*mulcp = 0;
if(gen1(g)) {
if(docode(hint, m->code, 1, 0))
return m;
print("multiply table failure %ld\n", v);
break;
}
}
/*
* try a recur followed by a shift
*/
g = 0;
while(!(v & 1)) {
g++;
v >>= 1;
}
if(g) {
m1 = mulcon0(v);
if(m1) {
strcpy(m->code, m1->code);
sprint(strchr(m->code, 0), "%c0", g+'a');
return m;
}
}
m->code[0] = 0;
return 0;
}
