static int spu_backing_mbox_read(struct spu_context *ctx, u32 * data) { u32 mbox_stat; int ret = 0; spin_lock(&ctx->csa.register_lock); mbox_stat = ctx->csa.prob.mb_stat_R; if (mbox_stat & 0x0000ff) { *data = ctx->csa.prob.pu_mb_R; ctx->csa.prob.mb_stat_R &= ~(0x0000ff); ctx->csa.spu_chnlcnt_RW[28] = 1; gen_spu_event(ctx, MFC_PU_MAILBOX_AVAILABLE_EVENT); ret = 4; } spin_unlock(&ctx->csa.register_lock); return ret; }
static int spu_backing_wbox_write(struct spu_context *ctx, u32 data) { int ret; spin_lock(&ctx->csa.register_lock); if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) { int slot = ctx->csa.spu_chnlcnt_RW[29]; int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8; BUG_ON(avail != (4 - slot)); ctx->csa.spu_mailbox_data[slot] = data; ctx->csa.spu_chnlcnt_RW[29] = ++slot; ctx->csa.prob.mb_stat_R &= ~(0x00ff00); ctx->csa.prob.mb_stat_R |= (((4 - slot) & 0xff) << 8); gen_spu_event(ctx, MFC_SPU_MAILBOX_WRITTEN_EVENT); ret = 4; } else {
static int spu_backing_ibox_read(struct spu_context *ctx, u32 * data) { int ret; spin_lock(&ctx->csa.register_lock); if (ctx->csa.prob.mb_stat_R & 0xff0000) { *data = ctx->csa.priv2.puint_mb_R; ctx->csa.prob.mb_stat_R &= ~(0xff0000); ctx->csa.spu_chnlcnt_RW[30] = 1; gen_spu_event(ctx, MFC_PU_INT_MAILBOX_AVAILABLE_EVENT); ret = 4; } else { ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR; ret = 0; } spin_unlock(&ctx->csa.register_lock); return ret; }
static int spu_backing_wbox_write(struct spu_context *ctx, u32 data) { int ret; spin_lock(&ctx->csa.register_lock); if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) { int slot = ctx->csa.spu_chnlcnt_RW[29]; int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8; /* We have space to write wbox_data. * Implementation note: the depth * of spu_mb_W is currently 4. */ BUG_ON(avail != (4 - slot)); ctx->csa.spu_mailbox_data[slot] = data; ctx->csa.spu_chnlcnt_RW[29] = ++slot; ctx->csa.prob.mb_stat_R = (((4 - slot) & 0xff) << 8); gen_spu_event(ctx, MFC_SPU_MAILBOX_WRITTEN_EVENT); ret = 4; } else {
static int spu_backing_mbox_read(struct spu_context *ctx, u32 * data) { u32 mbox_stat; int ret = 0; spin_lock(&ctx->csa.register_lock); mbox_stat = ctx->csa.prob.mb_stat_R; if (mbox_stat & 0x0000ff) { /* Read the first available word. * Implementation note: the depth * of pu_mb_R is currently 1. */ *data = ctx->csa.prob.pu_mb_R; ctx->csa.prob.mb_stat_R &= ~(0x0000ff); ctx->csa.spu_chnlcnt_RW[28] = 1; gen_spu_event(ctx, MFC_PU_MAILBOX_AVAILABLE_EVENT); ret = 4; } spin_unlock(&ctx->csa.register_lock); return ret; }
static int spu_backing_ibox_read(struct spu_context *ctx, u32 * data) { int ret; spin_lock(&ctx->csa.register_lock); if (ctx->csa.prob.mb_stat_R & 0xff0000) { /* Read the first available word. * Implementation note: the depth * of puint_mb_R is currently 1. */ *data = ctx->csa.priv2.puint_mb_R; ctx->csa.prob.mb_stat_R &= ~(0xff0000); ctx->csa.spu_chnlcnt_RW[30] = 1; gen_spu_event(ctx, MFC_PU_INT_MAILBOX_AVAILABLE_EVENT); ret = 4; } else { /* make sure we get woken up by the interrupt */ ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR; ret = 0; } spin_unlock(&ctx->csa.register_lock); return ret; }