bool DexRegion::HighProcess(OptCtx & oc) { CHAR const* ru_name = getRegionName(); g_indent = 0; SimpCtx simp; SIMP_if(&simp) = true; SIMP_doloop(&simp) = true; SIMP_dowhile(&simp) = true; SIMP_whiledo(&simp) = true; SIMP_switch(&simp) = false; SIMP_break(&simp) = true; SIMP_continue(&simp) = true; setIRList(simplifyStmtList(getIRList(), &simp)); ASSERT0(verify_simp(getIRList(), simp)); ASSERT0(verify_irs(getIRList(), NULL, this)); constructIRBBlist(); ASSERT0(verifyIRandBB(getBBList(), this)); //All IRs have been moved to each IRBB. setIRList(NULL); HighProcessImpl(oc); return true; }
void DexRegion::processSimply() { LOG("DexRegion::processSimply %s", getRegionName()); if (getIRList() == NULL) { return ; } OptCtx oc; OC_show_comp_time(oc) = g_show_comp_time; CHAR const* ru_name = getRegionName(); constructIRBBlist(); ASSERT0(verifyIRandBB(getBBList(), this)); //All IRs have been moved to each IRBB. setIRList(NULL); PassMgr * passmgr = initPassMgr(); ASSERT0(passmgr); ASSERT0(g_cst_bb_list); IR_CFG * cfg = (IR_CFG*)passmgr->registerPass(PASS_CFG); ASSERT0(cfg); cfg->initCfg(oc); ASSERT0(g_do_cfg_dom); cfg->LoopAnalysis(oc); destroyPassMgr(); //Do not allocate register. getPrno2Vreg()->clean(); getPrno2Vreg()->copy(*getDex2IR()->getPR2Vreg()); return; }
void AXLexer::lex(){ this->header = getHeader(); /* Read raw label first*/ this->rawLabel = getObjectTemp(); this->code = getIRList(); this->data = getDataSegment(); this->debug = getDINFO(); this->libDat = getLIBDATList(); this->structDat = getSTRUCTDATList(); this->structPrm = getSTRUCTPRMList(); this->hpiDat = getHPIDATList(); return; }
//This function outputs Prno2Vreg after Dex register allocation. bool DexRegion::process(OptCtx * oc) { if (getIRList() == NULL) { return true; } OC_show_comp_time(*oc) = g_show_comp_time; g_indent = 0; if (!g_silence) { LOG("DexRegion process %s", getRegionName()); } //note("\n==---- REGION_NAME:%s ----==", getRegionName()); prescan(getIRList()); PassMgr * passmgr = initPassMgr(); HighProcess(*oc); MiddleProcess(*oc); ASSERT0(getPassMgr()); PRSSAMgr * ssamgr = (PRSSAMgr*)passmgr->queryPass(PASS_PR_SSA_MGR); if (ssamgr != NULL && ssamgr->isSSAConstructed()) { ssamgr->destruction(); } if (!g_retain_pass_mgr_for_region) { //Destroy PassMgr. destroyPassMgr(); } if (!is_function()) { return true; } /////////////////////////////////////// //DO NOT REQUEST PASS AFTER THIS LINE// /////////////////////////////////////// BBList * bbl = getBBList(); if (bbl->get_elem_count() == 0) { return true; } ASSERT0(verifyIRandBB(bbl, this)); RefineCtx rf; RC_insert_cvt(rf) = false; //Do not insert cvt for DEX code. refineBBlist(bbl, rf); ASSERT0(verifyIRandBB(bbl, this)); if (g_do_dex_ra) { Prno2Vreg * original_prno2vreg = getDex2IR()->getPR2Vreg(); RA ra(this, getTypeIndexRep(), getParamNum(), getOrgVregNum(), getDex2IR()->getVreg2PR(), original_prno2vreg, &m_var2pr); LOG("\t\tdo DEX Register Allcation for '%s'", getRegionName()); ra.perform(*oc); updateRAresult(ra, *getPrno2Vreg()); } else { //Do not allocate register. getPrno2Vreg()->clean(); getPrno2Vreg()->copy(*getDex2IR()->getPR2Vreg()); } return true; }