unsigned Phy_Setup (XLlTemac *xlltemacp)
{
unsigned link_speed = 1000;
if (XLlTemac_GetPhysicalInterface(xlltemacp) ==
XTE_PHY_TYPE_RGMII_1_3) {
; /* Add PHY initialization code for RGMII 1.3 */
} else if (XLlTemac_GetPhysicalInterface(xlltemacp) ==
XTE_PHY_TYPE_RGMII_2_0) {
; /* Add PHY initialization code for RGMII 2.0 */
} else if (XLlTemac_GetPhysicalInterface(xlltemacp) ==
XTE_PHY_TYPE_SGMII) {
; /* Add PHY initialization code for SGMII */
} else if (XLlTemac_GetPhysicalInterface(xlltemacp) ==
XTE_PHY_TYPE_1000BASE_X) {
; /* Add PHY initialization code for 1000 Base-X */
}
/* set PHY <--> MAC data clock */
#ifdef CONFIG_LINKSPEED_AUTODETECT
link_speed = get_IEEE_phy_speed(xlltemacp);
xil_printf("auto-negotiated link speed: %d\r\n", link_speed);
#elif defined(CONFIG_LINKSPEED1000)
link_speed = 1000;
configure_IEEE_phy_speed(xlltemacp, link_speed);
xil_printf("link speed: %d\r\n", link_speed);
#elif defined(CONFIG_LINKSPEED100)
link_speed = 100;
configure_IEEE_phy_speed(xlltemacp, link_speed);
xil_printf("link speed: %d\r\n", link_speed);
#elif defined(CONFIG_LINKSPEED10)
link_speed = 10;
configure_IEEE_phy_speed(xlltemacp, link_speed);
xil_printf("link speed: %d\r\n", link_speed);
#endif
return link_speed;
}
unsigned Phy_Setup (XEmacPs *xemacpsp)
{
unsigned link_speed = 1000;
/* set PHY <--> MAC data clock */
#ifdef CONFIG_LINKSPEED_AUTODETECT
/* SLCR unlock */
*(unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
/* GEM module reset */
*(unsigned int *)(SLCR_ADDR_GEM_RST_CTRL) = 0x1;
*(unsigned int *)(SLCR_ADDR_GEM_RST_CTRL) = 0x0;
/* GEM1 1G clock configuration*/
*(unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) = SLCR_GEM_1G_CLK_CTRL_VALUE;
/* SLCR lock */
*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
link_speed = get_IEEE_phy_speed(xemacpsp);
xil_printf("auto-negotiated link speed: %d\r\n", link_speed);
if (link_speed == 1000) {
/* SLCR unlock */
*(unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
/* GEM module reset */
*(unsigned int *)(SLCR_ADDR_GEM_RST_CTRL) = 0x1;
*(unsigned int *)(SLCR_ADDR_GEM_RST_CTRL) = 0x0;
/* GEM1 1G clock configuration*/
*(unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) = SLCR_GEM_1G_CLK_CTRL_VALUE;
/* SLCR lock */
*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
configure_IEEE_phy_speed(xemacpsp, 1000);
} else if (link_speed == 100) {
/* SLCR unlock */
*(unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
/* GEM module reset */
*(unsigned int *)(SLCR_ADDR_GEM_RST_CTRL) = 0x1;
*(unsigned int *)(SLCR_ADDR_GEM_RST_CTRL) = 0x0;
/* GEM0 100M clock configuration*/
*(unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) = SLCR_GEM_100M_CLK_CTRL_VALUE;
/* SLCR lock */
*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
configure_IEEE_phy_speed(xemacpsp, 100);
} else if (link_speed == 10) {
/* SLCR unlock */
*(unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
/* GEM0 10M clock configuration*/
*(unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) = SLCR_GEM_10M_CLK_CTRL_VALUE;
/* SLCR lock */
*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
configure_IEEE_phy_speed(xemacpsp, 10);
}
#elif defined(CONFIG_LINKSPEED1000)
/* SLCR unlock */
*(unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
/* GEM module reset */
*(unsigned int *)(SLCR_ADDR_GEM_RST_CTRL) = 0x1;
*(unsigned int *)(SLCR_ADDR_GEM_RST_CTRL) = 0x0;
/* GEM1 1G clock configuration*/
*(unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) = SLCR_GEM_1G_CLK_CTRL_VALUE;
/* SLCR lock */
*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
link_speed = 1000;
configure_IEEE_phy_speed(xemacpsp, link_speed);
xil_printf("link speed: %d\r\n", link_speed);
#elif defined(CONFIG_LINKSPEED100)
/* SLCR unlock */
*(unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
/* GEM module reset */
*(unsigned int *)(SLCR_ADDR_GEM_RST_CTRL) = 0x1;
*(unsigned int *)(SLCR_ADDR_GEM_RST_CTRL) = 0x0;
/* GEM0 100M clock configuration*/
*(unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) = SLCR_GEM_100M_CLK_CTRL_VALUE;
/* SLCR lock */
*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
link_speed = 100;
configure_IEEE_phy_speed(xemacpsp, link_speed);
xil_printf("link speed: %d\r\n", link_speed);
#elif defined(CONFIG_LINKSPEED10)
/* SLCR unlock */
*(unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
/* GEM0 10M clock configuration*/
*(unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) = SLCR_GEM_10M_CLK_CTRL_VALUE;
/* SLCR lock */
*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
link_speed = 10;
configure_IEEE_phy_speed(xemacpsp, link_speed);
xil_printf("link speed: %d\r\n", link_speed);
#endif
return link_speed;
}
void
init_axiemac(xaxiemacif_s *xaxiemac, struct netif *netif)
{
int rdy;
unsigned mac_address = (unsigned)(netif->state);
unsigned link_speed = 1000;
unsigned options;
unsigned lock_message_printed = 0;
XAxiEthernet *xaxiemacp;
XAxiEthernet_Config *mac_config;
/* obtain config of this emac */
mac_config = lookup_config(mac_address);
xaxiemacp = &xaxiemac->axi_ethernet;
XAxiEthernet_CfgInitialize(xaxiemacp, mac_config, mac_config->BaseAddress);
options = XAxiEthernet_GetOptions(xaxiemacp);
options |= XAE_FLOW_CONTROL_OPTION;
#ifdef XLLTEMACIF_USE_JUMBO_FRAMES_EXPERIMENTAL
options |= XAE_JUMBO_OPTION;
#endif
options |= XAE_TRANSMITTER_ENABLE_OPTION;
options |= XAE_RECEIVER_ENABLE_OPTION;
options |= XAE_FCS_STRIP_OPTION;
options |= XAE_MULTICAST_OPTION;
XAxiEthernet_SetOptions(xaxiemacp, options);
XAxiEthernet_ClearOptions(xaxiemacp, ~options);
/* set mac address */
XAxiEthernet_SetMacAddress(xaxiemacp, (Xuint8*)(netif->hwaddr));
/* set PHY <--> MAC data clock */
#ifdef CONFIG_LINKSPEED_AUTODETECT
link_speed = get_IEEE_phy_speed(xaxiemacp);
xil_printf("auto-negotiated link speed: %d\r\n", link_speed);
#elif defined(CONFIG_LINKSPEED1000)
link_speed = 1000;
#elif defined(CONFIG_LINKSPEED100)
link_speed = 100;
#elif defined(CONFIG_LINKSPEED10)
link_speed = 10;
#endif
XAxiEthernet_SetOperatingSpeed(xaxiemacp, link_speed);
/* Setting the operating speed of the MAC needs a delay. */
{
volatile int wait;
for (wait=0; wait < 100000; wait++);
for (wait=0; wait < 100000; wait++);
}
#ifdef NOTNOW
/* in a soft temac implementation, we need to explicitly make sure that
* the RX DCM has been locked. See xps_ll_temac manual for details.
* This bit is guaranteed to be 1 for hard temac's
*/
lock_message_printed = 0;
while (!(XAxiEthernet_ReadReg(xaxiemacp->Config.BaseAddress, XAE_IS_OFFSET)
& XAE_INT_RXDCMLOCK_MASK)) {
int first = 1;
if (first) {
print("Waiting for RX DCM to lock..");
first = 0;
lock_message_printed = 1;
}
}
if (lock_message_printed)
print("RX DCM locked.\r\n");
#endif
/* start the temac */
XAxiEthernet_Start(xaxiemacp);
/* enable MAC interrupts */
XAxiEthernet_IntEnable(xaxiemacp, XAE_INT_RECV_ERROR_MASK);
}
