int timer_init(void)
{
struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
ulong tmr;
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
writel(0x0f00, &timers->TCFG0);
if (timer_load_val == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
*/
timer_load_val = get_PCLK() / (2 * 16 * 100);
timer_clk = get_PCLK() / (2 * 16);
}
/* load value for 10 ms timeout */
lastdec = timer_load_val;
writel(timer_load_val, &timers->TCNTB4);
/* auto load, manual update of Timer 4 */
tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->TCON);
/* auto load, start Timer 4 */
tmr = (tmr & ~0x0700000) | 0x0500000;
writel(tmr, &timers->TCON);
timestamp = 0;
return (0);
}
void Timer_StartEx(void)
{
struct s3c24x0_watchdog * const wdtregs = s3c24x0_get_base_watchdog();
wdtregs->WTCON=((get_PCLK()/1000000-1)<<8)|(0<<3)|(1<<2); // 16us
wdtregs->WTDAT=0xffff;
wdtregs->WTCNT=0xffff;
// 1/16/(65+1),interrupt enable,reset disable,watchdog enable
wdtregs->WTCON=((get_PCLK()/1000000-1)<<8)|(0<<3)|(1<<2)|(0<<0)|(1<<5);
}
void Timer_StartEx(void)
{
S3C24X0_WATCHDOG * const wdtregs = S3C24X0_GetBase_WATCHDOG();
wdtregs->WTCON=((get_PCLK()/1000000-1)<<8)|(0<<3)|(1<<2); // 16us
wdtregs->WTDAT=0xffff;
wdtregs->WTCNT=0xffff;
// 1/16/(65+1),interrupt enable,reset disable,watchdog enable
wdtregs->WTCON=((get_PCLK()/1000000-1)<<8)|(0<<3)|(1<<2)|(0<<0)|(1<<5);
}
int timer_init(void)
{
s3c64xx_timers *const timers = s3c64xx_get_base_timers();
/* use PWM Timer 4 because it has no output */
/*
* We use the following scheme for the timer:
* Prescaler is hard fixed at 167, divider at 1/4.
* This gives at PCLK frequency 66MHz approx. 10us ticks
* The timer is set to wrap after 100s, at 66MHz this obviously
* happens after 10,000,000 ticks. A long variable can thus
* keep values up to 40,000s, i.e., 11 hours. This should be
* enough for most uses:-) Possible optimizations: select a
* binary-friendly frequency, e.g., 1ms / 128. Also calculate
* the prescaler automatically for other PCLK frequencies.
*/
timers->TCFG0 = PRESCALER << 8;
gd->timer_rate_hz = get_PCLK() / PRESCALER * (100 / 4);
timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
/* load value for 10 ms timeout */
gd->lastinc = timers->TCNTB4 = gd->timer_rate_hz;
/* auto load, manual update of Timer 4 */
timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
TCON_4_UPDATE;
/* auto load, start Timer 4 */
timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
gd->timer_reset_value = 0;
return 0;
}
void serial_setbrg (void)
{
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
int i;
unsigned int reg = 0;
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * gd->baudrate) - 1;
/* FIFO enable, Tx/Rx FIFO clear */
uart->UFCON = 0x07;
uart->UMCON = 0x0;
/* Normal,No parity,1 stop,8 bit */
uart->ULCON = 0x3;
/*
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
uart->UCON = 0x245;
uart->UBRDIV = reg;
#ifdef CONFIG_HWFLOW
uart->UMCON = 0x1; /* RTS up */
#endif
for (i = 0; i < 100; i++);
}
int interrupt_init(void)
{
S3C64XX_TIMERS *const timers = S3C64XX_GetBase_TIMERS();
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
timers->TCFG0 = 0x0101;
if (timer_load_val == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
* alex: 20625 @ 66MHz
*/
timer_load_val = get_PCLK() / (2 * 16 * 100);
timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x40000;
}
/* load value for 10 ms timeout */
lastdec = timers->TCNTB4 = timer_load_val;
/* auto load, manual update of Timer 4 */
timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | TCON_4_UPDATE;
/* auto load, start Timer 4 */
timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
timestamp = 0;
return (0);
}
int timer_init (void)
{
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
timers->TCFG0 = 0x0f00;
if (timer_load_val == 0)
{
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
*/
timer_load_val = get_PCLK()/(2 * 16 * 100);
}
/* load value for 10 ms timeout */
lastdec = timers->TCNTB4 = timer_load_val;
/* auto load, manual update of Timer 4 */
timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
/* auto load, start Timer 4 */
timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
timestamp = 0;
return (0);
}
static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
{
ulong freq, pres = 16, div;
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
freq = get_i2c_clk();
#else
freq = get_PCLK();
#endif
/* calculate prescaler and divisor values */
if ((freq / pres / (16 + 1)) > speed)
/* set prescaler to 512 */
pres = 512;
div = 0;
while ((freq / pres / (div + 1)) > speed)
div++;
/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
/* init to SLAVE REVEIVE and set slaveaddr */
writel(0, &i2c->iicstat);
writel(slaveadd, &i2c->iicadd);
/* program Master Transmit (and implicit STOP) */
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
}
/* Set up the UART. */
static void uart_init(int minor)
{
int i;
unsigned int reg = 0;
/* enable UART0 */
rCLKCON|=0x100;
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * 115200) - 1;
/* FIFO enable, Tx/Rx FIFO clear */
rUFCON0 = 0x07;
rUMCON0 = 0x0;
/* Normal,No parity,1 stop,8 bit */
rULCON0 = 0x3;
/*
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
rUCON0 = 0x245;
rUBRDIV0 = reg;
for (i = 0; i < 100; i++);
}
void _serial_setbrg(const int dev_index)
{
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
unsigned int reg = 0;
int i;
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * gd->baudrate) - 1;
uart->UBRDIV = reg;
for (i = 0; i < 100; i++);
}
unsigned int Timer_StopEx(void)
{
int count;
struct s3c24x0_watchdog * const wdtregs = s3c24x0_get_base_watchdog();
struct s3c24x0_interrupt * const intregs = s3c24x0_get_base_interrupt();
wdtregs->WTCON=((get_PCLK()/1000000-1)<<8);
intregs->INTMSK|=BIT_WDT_AC97; //BIT_WDT;
intregs->INTSUBMSK |= (1<<13);
count=(0xffff-wdtregs->WTCNT)+(intCount*0xffff);
return ((unsigned int)count*16/1000000);
}
unsigned int Timer_StopEx(void)
{
int count;
S3C24X0_WATCHDOG * const wdtregs = S3C24X0_GetBase_WATCHDOG();
wdtregs->WTCON=((get_PCLK()/1000000-1)<<8);
intregs->INTMSK|=BIT_WDT_AC97; //BIT_WDT;
intregs->INTSUBMSK |= (1<<13);
count=(0xffff-wdtregs->WTCNT)+(intCount*0xffff);
return ((unsigned int)count*16/1000000);
}
void _serial_setbrg(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
unsigned int reg = 0;
int i;
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * gd->baudrate) - 1;
writel(reg, &uart->UBRDIV);
for (i = 0; i < 100; i++)
/* Delay */ ;
}
int timer_init(void)
{
struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
ulong tmr;
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
writel(0x0f00, &timers->tcfg0);
gd->timer_rate_hz = get_PCLK() /(2*16*100);
gd->tbl = get_PCLK() / (2 * 16);
/* load value for 10 ms timeout */
gd->lastinc = gd->timer_rate_hz;
writel(gd->timer_rate_hz, &timers->tcntb4);
/* auto load, manual update of timer 4 */
tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->tcon);
/* auto load, start timer 4 */
tmr = (tmr & ~0x0700000) | 0x0500000;
writel(tmr, &timers->tcon);
gd->timer_reset_value = 0;
return (0);
}
static void s3c64xx_serial_setbrg(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
u32 pclk = get_PCLK();
u32 baudrate = gd->baudrate;
int i;
i = (pclk / baudrate) % 16;
uart->UBRDIV = pclk / baudrate / 16 - 1;
uart->UDIVSLOT = udivslot[i];
for (i = 0; i < 100; i++)
barrier();
}
static int s3cmmc_set_ios(struct mmc *mmc)
{
struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
uint32_t divider = 0;
wide_bus = (mmc->bus_width == 4);
if (!mmc->clock)
return 0;
divider = DIV_ROUND_UP(get_PCLK(), mmc->clock);
if (divider)
divider--;
writel(divider, &sdi_regs->sdipre);
mdelay(125);
return 0;
}
/*
* Set up Timer 1
*/
void benchmark_timer_initialize( void )
{
uint32_t cr;
/* stop TIMER1*/
cr=rTCON & 0xFFFFF0FF;
rTCON=(cr | (0x0 << 8));
/* set MUX for Timer1 to 1/2 */
cr=rTCFG1 & 0xFFFFFF0F;
rTCFG1=(cr | (0<<4));
/* input freq=PLCK/2 Mhz*/
g_freq = get_PCLK() / 2000;
rTCNTB1 = 0xFFFF;
/* start TIMER1 with manual reload */
cr=rTCON & 0xFFFFF0FF;
rTCON=(cr | (0x1 << 9));
rTCON=(cr | (0x1 << 8));
g_start = rTCNTO1;
}
int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
int (*getwp)(struct mmc *))
{
struct s3cmmc_priv *priv;
struct mmc *mmc;
struct mmc_config *cfg;
priv = calloc(1, sizeof(*priv));
if (!priv)
return -ENOMEM;
cfg = &priv->cfg;
cfg->name = "S3C MMC";
cfg->ops = &s3cmmc_ops;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
cfg->f_min = 400000;
cfg->f_max = get_PCLK() / 2;
cfg->b_max = 0x80;
#if defined(CONFIG_S3C2410)
/*
* S3C2410 has some bug that prevents reliable
* operation at higher speed
*/
cfg->f_max /= 2;
#endif
mmc = mmc_create(cfg, priv);
if (!mmc) {
free(priv);
return -ENOMEM;
}
return 0;
}
static void print_cpu_speed(void)
{
printf("FCLK = %u MHz, HCLK = %u MHz, PCLK = %u MHz, UCLK = %u MHz\n",
get_FCLK()/MHZ, get_HCLK()/MHZ, get_PCLK()/MHZ, get_UCLK()/MHZ);
}
