/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
int dram_init(void)
{
unsigned int size0 = 0, size1 = 0;
u32 mtype, btype, rev = 0, cpu = 0;
#define NOT_EARLY 0
btype = get_board_type();
mtype = get_mem_type();
rev = get_cpu_rev();
cpu = get_cpu_type();
display_board_info(btype);
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
/* init other chip select */
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
}
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
#if CONFIG_NR_DRAM_BANKS > 1
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
gd->bd->bi_dram[1].size = size1;
#endif
return 0;
}
/*
* get_board_rev() - setup to pass kernel board revision information
* Returns:
* bit[0-3] Maximum cpu clock rate supported by onboard SoC
* 0000b - 300 MHz
* 0001b - 372 MHz
* 0010b - 408 MHz
* 0011b - 456 MHz
*/
u32 get_board_rev(void)
{
char *s;
u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
u32 rev = 0;
u32 btype;
s = getenv("maxcpuclk");
if (s)
maxcpuclk = simple_strtoul(s, NULL, 10);
if (maxcpuclk >= 456000000)
rev = 3;
else if (maxcpuclk >= 408000000)
rev = 2;
else if (maxcpuclk >= 372000000)
rev = 1;
btype = get_board_type();
if (btype == 1)
rev |= 0x100;
return rev;
}
void set_mux_conf_regs(void)
{
enum board_type board;
board = get_board_type(false);
enable_board_pin_mux(board);
}
/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
int dram_init(void)
{
#define NOT_EARLY 0
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
u32 mtype, btype;
btype = get_board_type();
mtype = get_mem_type();
#ifndef CONFIG_3430ZEBU
/* fixme... dont know why this func is crashing in ZeBu */
display_board_info(btype);
#endif
/* If a second bank of DDR is attached to CS1 this is
* where it can be started. Early init code will init
* memory on CS0.
*/
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
}
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
gd->bd->bi_dram[1].size = size1;
return 0;
}
void set_board_info(void)
{
char info[64];
snprintf(info, ARRAY_SIZE(info), "%u.%u", (s5p_cpu_rev & 0xf0) >> 4,
s5p_cpu_rev & 0xf);
setenv("soc_rev", info);
snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id);
setenv("soc_id", info);
#ifdef CONFIG_REVISION_TAG
snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev());
setenv("board_rev", info);
#endif
#ifdef CONFIG_OF_LIBFDT
const char *bdtype = "";
const char *bdname = CONFIG_SYS_BOARD;
#ifdef CONFIG_BOARD_TYPES
bdtype = get_board_type();
sprintf(info, "%s%s", bdname, bdtype);
setenv("boardname", info);
#endif
snprintf(info, ARRAY_SIZE(info), "%s%x-%s%s.dtb",
CONFIG_SYS_SOC, s5p_cpu_id, bdname, bdtype);
setenv("fdtfile", info);
#endif
}
/******************************************************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
*****************************************************************************/
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
u32 mtype, btype;
btype = get_board_type();
mtype = get_mem_type();
display_board_info(btype);
/* If a second bank of DDR is attached to CS1 this is
* where it can be started. Early init code will init
* memory on CS0.
*/
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED))
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
gd->bd->bi_dram[1].size = size1;
return 0;
}
int checkboard(void)
{
const char *board_info;
board_info = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
printf("Board: %s\n", board_info ? board_info : "unknown");
#ifdef CONFIG_BOARD_TYPES
board_info = get_board_type();
printf("Model: %s\n", board_info ? board_info : "unknown");
#endif
return 0;
}
void am33xx_spl_board_init(void)
{
/* debug print detect status */
(void)get_board_type(true);
/* Get the frequency */
/* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
dpll_mpu_opp100.m = MPUPLL_M_1000;
if (i2c_probe(TPS65217_CHIP_PM))
return;
/* Set the USB Current Limit */
if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
TPS65217_USB_INPUT_CUR_LIMIT_MASK))
puts("! tps65217_reg_write: could not set USB limit\n");
/* Set the Core Voltage (DCDC3) to 1.125V */
if (tps65217_voltage_update(TPS65217_DEFDCDC3,
TPS65217_DCDC_VOLT_SEL_1125MV)) {
puts("! tps65217_reg_write: could not set Core Voltage\n");
return;
}
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* Set the MPU Voltage (DCDC2) */
if (tps65217_voltage_update(TPS65217_DEFDCDC2,
TPS65217_DCDC_VOLT_SEL_1325MV)) {
puts("! tps65217_reg_write: could not set MPU Voltage\n");
return;
}
/*
* Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
* Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
*/
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
puts("! tps65217_reg_write: could not set LDO3\n");
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
puts("! tps65217_reg_write: could not set LDO4\n");
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
/*****************************************
* Routine: board_init
* Description: Early hardware init.
*****************************************/
int board_init(void)
{
u32 rev ;
DECLARE_GLOBAL_DATA_PTR;
gpmc_init(); /* in SRAM or SDRM, finish GPMC */
rev = get_board_type();
if ((rev == BOARD_H4_SDP)) {
gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */
} else {
gd->bd->bi_arch_number = MACH_TYPE_OMAP_2430SDP; /* board id for linux */
}
gd->bd->bi_boot_params = (OMAP24XX_SDRC_CS0 + 0x100); /* adress of boot parameters */
return 0;
}
/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
u32 mtype, btype;
#ifdef CONFIG_DRIVER_OMAP24XX_I2C
u8 data;
#endif
#define NOT_EARLY 0
#ifdef CONFIG_DRIVER_OMAP24XX_I2C
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
select_bus(1, CFG_I2C_SPEED); /* select bus with T2 on it */
#endif
btype = get_board_type();
mtype = get_mem_type();
display_board_info(btype);
#ifdef CONFIG_DRIVER_OMAP24XX_I2C
if (btype == BOARD_SDP_2430_T2) {
/* Enable VMODE following voltage switching */
data = 0x24; /* set the floor voltage to 1.05v */
i2c_write(I2C_TRITON2, 0xBB, 1, &data, 1);
data = 0x38; /* set the roof voltage to 1.3V */
i2c_write(I2C_TRITON2, 0xBC, 1, &data, 1);
data = 0x0; /* set jump mode for VDD voltage transition */
i2c_write(I2C_TRITON2, 0xBD, 1, &data, 1);
data = 1; /* enable voltage scaling */
i2c_write(I2C_TRITON2, 0xBA, 1, &data, 1);
}
#endif
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
/* init other chip select and map CS1 right after CS0 */
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
}
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
gd->bd->bi_dram[1].size = size1;
return 0;
}
/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0=0,size1=0;
u32 mtype, btype, rev, cpu;
u8 chg_on = 0x5; /* enable charge of back up battery */
u8 vmode_on = 0x8C;
#define NOT_EARLY 0
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
btype = get_board_type();
mtype = get_mem_type();
rev = get_cpu_rev();
cpu = get_cpu_type();
display_board_info(btype);
if (btype == BOARD_H4_MENELAUS){
update_mux(btype,mtype); /* combo part on menelaus */
i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
}
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
}
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
else /* ES2 and above can remap at 32MB granularity */
gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
gd->bd->bi_dram[1].size = size1;
return 0;
}
/**********************************************
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
int dram_init(void)
{
#define NOT_EARLY 0
//20101215_Peter ++
//#define DEBUG
#if defined (CONFIG_EPXX_DDR_512MB)
#define EARLY_INIT 1
#endif
//20101215_Peter --
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
u32 mtype, btype;
btype = get_board_type();
mtype = get_mem_type();
#ifndef CONFIG_3430ZEBU
/* fixme... dont know why this func is crashing in ZeBu */
display_board_info(btype);
#endif
/* If a second bank of DDR is attached to CS1 this is
* where it can be started. Early init code will init
* memory on CS0.
*/
if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
//20101215_Peter ++
#if defined (CONFIG_EPXX_DDR_512MB)
do_sdrc_init(SDRC_CS1_OSET, EARLY_INIT);
make_cs1_contiguous();
#else
do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
#endif
//20101215_Peter --
}
#ifdef DEBUG
{
unsigned int reg = 0;
reg = __raw_readl(SDRC_MCFG_0);
printf("SDRC_MCFG_0: %08x\n", reg);
reg = __raw_readl(SDRC_MCFG_1);
printf("SDRC_MCFG_1: %08x\n", reg);
reg = __raw_readl(SDRC_ACTIM_CTRLA_0);
__raw_writel(reg, SDRC_ACTIM_CTRLA_1);
printf("SDRC_ACTIM_CTRLA_0: %08x\n", reg);
reg = __raw_readl(SDRC_ACTIM_CTRLB_0);
__raw_writel(reg, SDRC_ACTIM_CTRLB_1);
printf("SDRC_ACTIM_CTRLB_0: %08x\n", reg);
reg = __raw_readl(SDRC_ACTIM_CTRLA_1);
printf("SDRC_ACTIM_CTRLA_1: %08x\n", reg);
reg = __raw_readl(SDRC_ACTIM_CTRLB_1);
printf("SDRC_ACTIM_CTRLB_1: %08x\n", reg);
reg = __raw_readl(SDRC_MANUAL_0);
printf("SDRC_MANUAL_0: %08x\n", reg);
reg = __raw_readl(SDRC_MANUAL_1);
printf("SDRC_MANUAL_1: %08x\n", reg);
reg = __raw_readl(SDRC_MR_0);
printf("SDRC_MR_0: %08x\n", reg);
reg = __raw_readl(SDRC_MR_1);
printf("SDRC_MR_1: %08x\n", reg);
reg = __raw_readl(SDRC_RFR_CTRL_0);
__raw_writel(reg, SDRC_RFR_CTRL_1);
printf("SDRC_RFR_CTRL_0: %08x\n", reg);
reg = __raw_readl(SDRC_RFR_CTRL_1);
printf("SDRC_RFR_CTRL_1: %08x\n", reg);
reg = __raw_readl(CONTROL_PROG_IO0);
printf("CONTROL_PROG_IO0: %08x\n", reg);
reg = __raw_readl(CONTROL_PROG_IO1);
printf("CONTROL_PROG_IO1: %08x\n", reg);
reg = __raw_readl(SDRC_DLLA_CTRL);
printf("SDRC_DLLA_CTRL: %08x\n", reg);
}
#endif
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
gd->bd->bi_dram[1].size = size1;
return 0;
}
int xcmd_set_bdinfo(char * buffer)
{
uint16_t data,idx;
uint8_t bdtype;
CalibMsg *msg = (CalibMsg *)buffer;
msg->seq_no = g_seq_no;
msg->dest = 0xffff;//g_dest;
msg->inst[0].cmd=XCOMMAND_CALIBRATION;
msg->inst[0].subcmd=CALIB_SETBDINFO;
calib_set_header(buffer);
if (g_argument)
{
idx=GetDataValue(g_argument,0);
if(idx==0xffff)
{
printf("error: Value type is not right.\n");
return 0;
}
switch(idx)
{
case 0:
case 1:
msg->inst[0].param.calibration.valtype=(uint8_t)(idx);
data=GetDataValue(g_argument,1);
if(data==0xffff)
{
printf("error: Info type is not right.\n");
return 0;
}
msg->inst[0].param.calibration.infotype=(uint16_t)(data);
data=GetDataValue(g_argument,2);
if(data==0xffff || data>255)
{
printf("error: Offset is not right.\n");
return 0;
}
msg->inst[0].param.calibration.offset=(uint8_t)(data);
data=GetDataValue(g_argument,3);
if(data==0xffff)
{
printf("error: Value is not right.\n");
return 0;
}
msg->inst[0].param.calibration.data=(uint16_t)(data);
break;
case 2:
GetDataChar(g_argument,1);
bdtype=get_board_type(value);
if(bdtype==0)
{
printf("error: Board name is not right.\n");
return 0;
}
data=GetDataValue(g_argument,3);
if(data==0xffff)
{
printf("error: Value is not right.\n");
return 0;
}
msg->inst[0].param.calibration.data=(uint16_t)(data);
GetDataChar(g_argument,2);
name=get_value_str(bdtype,value);
if(name==NULL)
{
printf("\n error: Could not find the name in the table.\n");
return 0;
}
data=GetDataValue((char*)name,0);
if(idx==0xffff)
{
printf("error: Value type is not right.\n");
return 0;
}
msg->inst[0].param.calibration.valtype=(uint8_t)(data);
data=GetDataValue((char*)name,1);
if(data==0xffff)
{
printf("error: Info type is not right.\n");
return 0;
}
msg->inst[0].param.calibration.infotype=(uint16_t)(data);
data=GetDataValue((char*)name,2);
if(data==0xffff || data>255)
{
printf("error: Offset is not right.\n");
return 0;
}
msg->inst[0].param.calibration.offset=(uint8_t)(data);
break;
default:
break;
}
}
else
{
printf("error: No right parameters found.\n");
return 0;
}
return sizeof(CalibMsg);
}
static int
sscape_download_boot (struct sscape_info *devc, unsigned char *block, int size, int flag)
{
unsigned long flags;
unsigned char temp;
int done, timeout_val;
static unsigned char codec_dma_bits = 0;
if (flag & CPF_FIRST)
{
/*
* First block. Have to allocate DMA and to reset the board
* before continuing.
*/
save_flags (flags);
cli ();
codec_dma_bits = sscape_read (devc, GA_CDCFG_REG);
#if 0
sscape_write (devc, GA_CDCFG_REG,
codec_dma_bits & ~0x08); /* Disable codec DMA */
#endif
if (devc->dma_allocated == 0)
{
devc->dma_allocated = 1;
}
restore_flags (flags);
sscape_write (devc, GA_HMCTL_REG,
(temp = sscape_read (devc, GA_HMCTL_REG)) & 0x3f); /*Reset */
for (timeout_val = 10000; timeout_val > 0; timeout_val--)
sscape_read (devc, GA_HMCTL_REG); /* Delay */
/* Take board out of reset */
sscape_write (devc, GA_HMCTL_REG,
(temp = sscape_read (devc, GA_HMCTL_REG)) | 0x80);
}
/*
* Transfer one code block using DMA
*/
memcpy (audio_devs[devc->my_audiodev]->dmap_out->raw_buf, block, size);
save_flags (flags);
cli ();
/******** INTERRUPTS DISABLED NOW ********/
do_dma (devc, SSCAPE_DMA_A,
audio_devs[devc->my_audiodev]->dmap_out->raw_buf_phys,
size, DMA_MODE_WRITE);
/*
* Wait until transfer completes.
*/
sscape_sleep_flag.flags = WK_NONE;
done = 0;
timeout_val = 100;
while (!done && timeout_val-- > 0)
{
int resid;
{
unsigned long tlimit;
if (1)
current_set_timeout (tlimit = jiffies + (1));
else
tlimit = (unsigned long) -1;
sscape_sleep_flag.flags = WK_SLEEP;
module_interruptible_sleep_on (&sscape_sleeper);
if (!(sscape_sleep_flag.flags & WK_WAKEUP))
{
if (jiffies >= tlimit)
sscape_sleep_flag.flags |= WK_TIMEOUT;
}
sscape_sleep_flag.flags &= ~WK_SLEEP;
};
clear_dma_ff (devc->dma);
if ((resid = get_dma_residue (devc->dma)) == 0)
{
done = 1;
}
}
restore_flags (flags);
if (!done)
return 0;
if (flag & CPF_LAST)
{
/*
* Take the board out of reset
*/
outb (0x00, PORT (HOST_CTRL));
outb (0x00, PORT (MIDI_CTRL));
temp = sscape_read (devc, GA_HMCTL_REG);
temp |= 0x40;
sscape_write (devc, GA_HMCTL_REG, temp); /* Kickstart the board */
/*
* Wait until the ODB wakes up
*/
save_flags (flags);
cli ();
done = 0;
timeout_val = 5 * HZ;
while (!done && timeout_val-- > 0)
{
{
unsigned long tlimit;
if (1)
current_set_timeout (tlimit = jiffies + (1));
else
tlimit = (unsigned long) -1;
sscape_sleep_flag.flags = WK_SLEEP;
module_interruptible_sleep_on (&sscape_sleeper);
if (!(sscape_sleep_flag.flags & WK_WAKEUP))
{
if (jiffies >= tlimit)
sscape_sleep_flag.flags |= WK_TIMEOUT;
}
sscape_sleep_flag.flags &= ~WK_SLEEP;
};
if (inb (PORT (HOST_DATA)) == 0xff) /* OBP startup acknowledge */
done = 1;
}
sscape_write (devc, GA_CDCFG_REG, codec_dma_bits);
restore_flags (flags);
if (!done)
{
printk ("SoundScape: The OBP didn't respond after code download\n");
return 0;
}
save_flags (flags);
cli ();
done = 0;
timeout_val = 5 * HZ;
while (!done && timeout_val-- > 0)
{
{
unsigned long tlimit;
if (1)
current_set_timeout (tlimit = jiffies + (1));
else
tlimit = (unsigned long) -1;
sscape_sleep_flag.flags = WK_SLEEP;
module_interruptible_sleep_on (&sscape_sleeper);
if (!(sscape_sleep_flag.flags & WK_WAKEUP))
{
if (jiffies >= tlimit)
sscape_sleep_flag.flags |= WK_TIMEOUT;
}
sscape_sleep_flag.flags &= ~WK_SLEEP;
};
if (inb (PORT (HOST_DATA)) == 0xfe) /* Host startup acknowledge */
done = 1;
}
restore_flags (flags);
if (!done)
{
printk ("SoundScape: OBP Initialization failed.\n");
return 0;
}
printk ("SoundScape board of type %d initialized OK\n",
get_board_type (devc));
set_control (devc, CTL_MASTER_VOL, 100);
set_control (devc, CTL_SYNTH_VOL, 100);
#ifdef SSCAPE_DEBUG3
/*
* Temporary debugging aid. Print contents of the registers after
* downloading the code.
*/
{
int i;
for (i = 0; i < 13; i++)
printk ("I%d = %02x (new value)\n", i, sscape_read (devc, i));
}
#endif
}
return 1;
}
static int
sscape_download_boot(struct sscape_info * devc, u_char *block, int size, int flag)
{
u_long flags;
u_char temp;
int done, timeout_val;
if (flag & CPF_FIRST) {
/*
* First block. Have to allocate DMA and to reset the board
* before continuing.
*/
flags = splhigh();
if (devc->dma_allocated == 0) {
devc->dma_allocated = 1;
}
splx(flags);
sscape_write(devc, GA_HMCTL_REG,
(temp = sscape_read(devc, GA_HMCTL_REG)) & 0x3f); /* Reset */
for (timeout_val = 10000; timeout_val > 0; timeout_val--)
sscape_read(devc, GA_HMCTL_REG); /* Delay */
/* Take board out of reset */
sscape_write(devc, GA_HMCTL_REG,
(temp = sscape_read(devc, GA_HMCTL_REG)) | 0x80);
}
/*
* Transfer one code block using DMA
*/
bcopy(block, audio_devs[devc->my_audiodev]->dmap_out->raw_buf, size);
flags = splhigh();
/******** INTERRUPTS DISABLED NOW ********/
do_dma(devc, SSCAPE_DMA_A,
audio_devs[devc->my_audiodev]->dmap_out->raw_buf_phys,
size, 1);
/*
* Wait until transfer completes.
*/
sscape_sleep_flag.aborting = 0;
sscape_sleep_flag.mode = WK_NONE;
done = 0;
timeout_val = 100;
while (!done && timeout_val-- > 0) {
int chn;
sscape_sleeper = &chn;
DO_SLEEP(chn, sscape_sleep_flag, 1);
done = 1;
}
splx(flags);
if (!done)
return 0;
if (flag & CPF_LAST) {
/*
* Take the board out of reset
*/
outb(PORT(HOST_CTRL), 0x00);
outb(PORT(MIDI_CTRL), 0x00);
temp = sscape_read(devc, GA_HMCTL_REG);
temp |= 0x40;
sscape_write(devc, GA_HMCTL_REG, temp); /* Kickstart the board */
/*
* Wait until the ODB wakes up
*/
flags = splhigh();
done = 0;
timeout_val = 5 * hz;
while (!done && timeout_val-- > 0) {
int chn;
sscape_sleeper = &chn;
DO_SLEEP(chn, sscape_sleep_flag, 1);
if (inb(PORT(HOST_DATA)) == 0xff) /* OBP startup acknowledge */
done = 1;
}
splx(flags);
if (!done) {
printf("SoundScape: The OBP didn't respond after code download\n");
return 0;
}
flags = splhigh();
done = 0;
timeout_val = 5 * hz;
while (!done && timeout_val-- > 0) {
int chn;
sscape_sleeper = &chn;
DO_SLEEP(chn, sscape_sleep_flag, 1);
if (inb(PORT(HOST_DATA)) == 0xfe) /* Host startup acknowledge */
done = 1;
}
splx(flags);
if (!done) {
printf("SoundScape: OBP Initialization failed.\n");
return 0;
}
printf("SoundScape board of type %d initialized OK\n",
get_board_type(devc));
set_control(devc, CTL_MASTER_VOL, 100);
set_control(devc, CTL_SYNTH_VOL, 100);
#ifdef SSCAPE_DEBUG3
/*
* Temporary debugging aid. Print contents of the registers
* after downloading the code.
*/
{
int i;
for (i = 0; i < 13; i++)
printf("I%d = %02x (new value)\n", i, sscape_read(devc, i));
}
#endif
}
return 1;
}
int board_eth_init(bd_t *bis)
{
int ecode, rv, n;
uint8_t mac_addr[6];
struct board_eeconfig header;
__maybe_unused enum board_type board;
/* Default manufacturing address; used when no EE or invalid */
n = 0;
mac_addr[0] = 0;
mac_addr[1] = 0x20;
mac_addr[2] = 0x18;
mac_addr[3] = 0x1C;
mac_addr[4] = 0x00;
mac_addr[5] = 0x01;
ecode = read_eeprom(&header);
/* if we have a valid EE, get mac address from there */
if ((ecode == 0) &&
is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
}
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!getenv("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#ifdef CONFIG_DRIVER_TI_CPSW
board = get_board_type(false);
/* Rev.A uses 10/100 PHY in mii mode */
if (board == BAV335A) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
}
/* Rev.B (default) uses GB PHY in rmii mode */
else {
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
= PHY_INTERFACE_MODE_RGMII;
}
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
#endif
#endif
return n;
}
void iomux_debug_set(void)
{
int i = 0;
unsigned int uregv = 0;
struct iocfg_lp *iocfg_lookups = NULL;
get_active_io_cfglp();
iocfg_lookups = p_active_io_cfglp;
for (i = 0; i < IO_LIST_LENGTH; i++) {
uregv = ((iocfg_lookups[i].ugpiog<<3)+iocfg_lookups[i].ugpio_bit);
/*uart0 suspend printk*/
if ((0 == console_suspend_enabled)
&& ((uregv >= 117) && (uregv <= 120)))
continue;
if (E_BOARD_TYPE_PLATFORM == get_board_type()) {
/*oem board*/
if ((uregv == 40) || (uregv == 83))
continue;
if ((uregv >= 129) && (uregv <= 132))
continue;
if ((uregv >= 137) && (uregv <= 140))
continue;
} else {
if ((uregv == 145) || (uregv == 146))
continue;
}
uregv = readl(IOC_BASE_ADDR + (iocfg_lookups[i].uiomg_off));
if (iocfg_lookups[i].iomg_val != -1) {
if ((uregv&0x1) == iocfg_lookups[i].iomg_val)
writel(uregv, IOC_BASE_ADDR + (iocfg_lookups[i].uiomg_off));
else
writel(iocfg_lookups[i].iomg_val, IOC_BASE_ADDR + (iocfg_lookups[i].uiomg_off));
}
uregv = readl(IOC_BASE_ADDR + 0x800 + (iocfg_lookups[i].uiocg_off));
if (iocfg_lookups[i].iocg_val != -1) {
if ((uregv&0x3) == iocfg_lookups[i].iocg_val)
writel(uregv, IOC_BASE_ADDR + 0x800 + (iocfg_lookups[i].uiocg_off));
else
writel(iocfg_lookups[i].iocg_val, IOC_BASE_ADDR + 0x800 + (iocfg_lookups[i].uiocg_off));
}
uregv = readl(GPIO_DIR(iocfg_lookups[i].ugpiog));
uregv &= ~GPIO_BIT(1, iocfg_lookups[i].ugpio_bit);
uregv |= GPIO_BIT(iocfg_lookups[i].gpio_dir, iocfg_lookups[i].ugpio_bit);
writel(uregv, GPIO_DIR(iocfg_lookups[i].ugpiog));
uregv = readl(GPIO_DIR(iocfg_lookups[i].ugpiog));
uregv = readl(GPIO_DATA(iocfg_lookups[i].ugpiog));
uregv &= ~GPIO_BIT(1, iocfg_lookups[i].ugpio_bit);
uregv |= GPIO_BIT(iocfg_lookups[i].gpio_val, iocfg_lookups[i].ugpio_bit);
writel(uregv, GPIO_DATA(iocfg_lookups[i].ugpiog));
}
}
static int show_cpuinfo(struct seq_file *m, void *v)
{
unsigned long n = (unsigned long) v - 1;
unsigned int version = cpu_data[n].processor_id;
unsigned int fp_vers = cpu_data[n].fpu_id;
char fmt [64];
int i;
struct thread_struct *mc_thread = ¤t->thread;
#ifdef CONFIG_SMP
if (!cpu_isset(n, cpu_online_map))
return 0;
#endif
/* For Magiccode */
/* For Magiccode, when current process uses emulated ARM native code: */
if (mc_thread->mcflags != CPU_MIPS) {
/* mimic cpuinfo of 2012 Nexus7 with NVidia Tegra3 T30L cpu */
seq_printf(m, "Processor\t: ARMv7 Processor rev 9 (v7l)\n");
seq_printf(m, "processor\t: 0\n");
seq_printf(m, "BogoMIPS\t: 1001.88\n\n");
/* show just one processor core */
seq_printf(m, "Features\t: swp half thumb fastmult vfp ");
if (mc_thread->mcflags == CPU_ARM_NEON)
seq_printf(m, "edsp neon ");
seq_printf(m, "vfpv3\n");
/* no thumbee or tls feature */
seq_printf(m, "CPU implementer\t: 0x41\n"); /* ARM */
seq_printf(m, "CPU architecture: 7\n");
seq_printf(m, "CPU variant\t: 0x2\n");
seq_printf(m, "CPU part\t: 0xc09\n"); /* Cortex-A9 */
seq_printf(m, "CPU revision\t: 9\n");
seq_printf(m, "\n");
return 0;
}
else {
/*
* For the first processor also print the system type
*/
unsigned int detected = 0;
rcu_read_lock();
if ((strcmp(current->parent->comm, "tv.apad:vplayer") == 0) ||
(strcmp(current->comm, "tv.apad:vplayer") == 0)) {
detected = 1;
}
rcu_read_unlock();
if (n == 0) {
seq_printf(m, "system type\t\t: %s\n", get_system_type());
if (mips_get_machine_name())
seq_printf(m, "machine\t\t\t: %s\n",
mips_get_machine_name());
}
if (detected == 0) {
seq_printf(m, "processor\t\t: %ld\n", n);
} else {
seq_printf(m, "processor\t\t: ARMv7 swp half thumb fastmult vfp edsp neon vfpv3 %ld\n ", n);
}
sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
seq_printf(m, fmt, __cpu_name[n],
(version >> 4) & 0x0f, version & 0x0f,
(fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
cpu_data[n].udelay_val / (500000/HZ),
(cpu_data[n].udelay_val / (5000/HZ)) % 100);
seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
if (detected == 0) {
seq_printf(m, "microsecond timers\t: %s\n",
cpu_has_counter ? "yes" : "no");
}
seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
seq_printf(m, "extra interrupt vector\t: %s\n",
cpu_has_divec ? "yes" : "no");
seq_printf(m, "hardware watchpoint\t: %s",
cpu_has_watch ? "yes, " : "no\n");
if (cpu_has_watch) {
seq_printf(m, "count: %d, address/irw mask: [",
cpu_data[n].watch_reg_count);
for (i = 0; i < cpu_data[n].watch_reg_count; i++)
seq_printf(m, "%s0x%04x", i ? ", " : "" ,
cpu_data[n].watch_reg_masks[i]);
seq_printf(m, "]\n");
}
seq_printf(m, "microMIPS\t\t: %s\n", cpu_has_mmips ? "yes" : "no");
seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s%s\n",
cpu_has_mips16 ? " mips16" : "",
cpu_has_mdmx ? " mdmx" : "",
cpu_has_mips3d ? " mips3d" : "",
cpu_has_smartmips ? " smartmips" : "",
cpu_has_dsp ? " dsp" : "",
cpu_has_mipsmt ? " mt" : "",
cpu_has_mxu ? " mxu" : ""
);
seq_printf(m, "shadow register sets\t: %d\n",
cpu_data[n].srsets);
seq_printf(m, "kscratch registers\t: %d\n",
hweight8(cpu_data[n].kscratch_mask));
seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
cpu_has_vce ? "%u" : "not available");
seq_printf(m, fmt, 'D', vced_count);
seq_printf(m, fmt, 'I', vcei_count);
/* Android requires 'Hardware' to setup the init.%hardware%.rc */
seq_printf(m, "Hardware\t\t: %s\n", get_board_type());
seq_printf(m, "\n");
}
return 0;
}
