unsigned long acpi_fill_madt(unsigned long current)
{
get_bus_conf();
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write SB600 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edge-triggered, Active high */
/* create all subtables for processors */
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
/* 1: LINT1 connect to NMI */
return current;
}
unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acpi_rsdp_t *rsdp)
{
unsigned long current;
acpi_header_t *ssdtx;
const void *p;
size_t p_size;
int i;
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */
start = ALIGN(start, 16);
current = start;
/* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
const char *file_name;
if((sysconf.pci1234[i] & 1) != 1 ) continue;
u8 c;
if(i < 7) {
c = (u8) ('4' + i - 1);
}
else {
c = (u8) ('A' + i - 1 - 6);
}
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */
ssdtx = (acpi_header_t *)current;
switch(sysconf.hcid[i]) {
case 1: /* 8132 */
file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml";
break;
case 2: /* 8151 */
file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml";
break;
case 3: /* 8131 */
file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml";
break;
default:
continue;
}
p = cbfs_boot_map_with_leak(
file_name,
CBFS_TYPE_RAW, &p_size);
if (!p || p_size < sizeof(acpi_header_t))
continue;
memcpy(ssdtx, p, sizeof(acpi_header_t));
current += ssdtx->length;
memcpy(ssdtx, p, ssdtx->length);
update_ssdtx((void *)ssdtx, i);
ssdtx->checksum = 0;
ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
acpi_add_table(rsdp, ssdtx);
}
return current;
}
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
unsigned int slot_num, sbdn;
uint8_t *v;
uint8_t sum = 0;
int i;
/* Will find out all bus num and apic that share with mptable.c
* and mptable.c and acpi_tables.c.
*/
get_bus_conf();
sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
/* This table must be between 0xf0000 and 0x100000. */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_mcp55[0];
pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x10de;
pirq->rtr_device = 0x0370; /* TODO: Hm, getpir suggests 0x0364 !? */
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
/* PCI bridge (00:06.0) */
write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++;
slot_num++;
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum)
pirq->checksum = sum;
printk(BIOS_INFO, "done.\n");
return (unsigned long)pirq_info;
}
unsigned long acpi_fill_madt(unsigned long current)
{
unsigned int gsi_base = 0x18;
struct mb_sysconf_t *m;
//extern unsigned char bus_mcp55[8];
//extern unsigned apicid_mcp55;
unsigned sbdn;
struct resource *res;
device_t dev;
get_bus_conf();
sbdn = sysconf.sbdn;
m = sysconf.mb;
/* Create all subtables for processors. */
current = acpi_create_madt_lapics(current);
/* Write SB IOAPIC. */
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
m->apicid_mcp55, res->base, 0);
}
}
/* Write NB IOAPIC. */
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x12,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
m->apicid_mcp55++, res->base, gsi_base);
}
}
/* IRQ9 ACPI active low. */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
/* IRQ0 -> APIC IRQ2. */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0x0);
/* Create all subtables for processors. */
current = acpi_create_madt_lapic_nmis(current,
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
return current;
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
u32 dword;
u8 byte;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
/* APIC */
unsigned long acpi_fill_madt(unsigned long current)
{
device_t dev;
struct resource *res;
get_bus_conf();
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write NVIDIA CK804 IOAPIC. */
dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
ASSERT(dev != NULL);
res = find_resource(dev, PCI_BASE_ADDRESS_1);
ASSERT(res != NULL);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
res->base, 0);
/* Initialize interrupt mapping if mptable.c didn't. */
#if (!CONFIG_GENERATE_MP_TABLE)
pci_write_config32(dev, 0x7c, 0x0120d218);
pci_write_config32(dev, 0x80, 0x12008a00);
pci_write_config32(dev, 0x84, 0x0000007d);
#endif
/* IRQ9 */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edge-triggered, Active high */
/* create all subtables for processors */
/* acpi_create_madt_lapic_nmis returns current, not size. */
current = acpi_create_madt_lapic_nmis(current, 5, 1);
return current;
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
u32 dword;
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
/* Initialize interrupt mapping */
/* aza */
byte = pci_read_config8(dev, 0x63);
byte &= 0xf8;
byte |= 0; /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* changes added to match acpi tables */
PCI_INT(0x0, 0x02, 0x0, 0x12);
PCI_INT(0x0, 0x03, 0x0, 0x13);
PCI_INT(0x0, 0x04, 0x0, 0x10);
PCI_INT(0x0, 0x09, 0x0, 0x11);
PCI_INT(0x0, 0x0A, 0x0, 0x12);
PCI_INT(0x0, 0x12, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x3, 0x13);
PCI_INT(0x0, 0x13, 0x2, 0x10);
PCI_INT(0x0, 0x13, 0x2, 0x11);
PCI_INT(0x0, 0x14, 0x1, 0x11);
PCI_INT(0x0, 0x14, 0x3, 0x13);
PCI_INT(0x1, 0x05, 0x2, 0x10);
PCI_INT(0x1, 0x05, 0x3, 0x11);
PCI_INT(0x2, 0x00, 0x0, 0x12);
PCI_INT(0x2, 0x00, 0x1, 0x13);
PCI_INT(0x2, 0x00, 0x2, 0x10);
PCI_INT(0x2, 0x00, 0x3, 0x11);
/* RS780 PCI to PCI bridge (PCIE port 4) */
PCI_INT(0x0, 0x09, 0x0, 0x11);
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
PCI_INT(0x0, 0x14, 0x2, 0x12);
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(0x1, 0x5, 0x0, 0x12); /* VGA */
PCI_INT(0x1, 0x5, 0x1, 0x13); /* Audio */
/* PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); */ /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
/* PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); */
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
/* PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); */
PCI_INT(0x3, 0x0, 0x0, 0x11); /* NIC */
/* PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
#if CONFIG_ACPI_SSDTX_NUM >= 1
acpi_header_t *ssdtx;
void *p;
int i;
#endif
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */
start = ALIGN(start, 16);
current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt);
/*
* We explicitly add these tables later on:
*/
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdp, madt);
/* SRAT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) current;
acpi_create_srat(srat);
current += srat->header.length;
acpi_add_table(rsdp, srat);
/* SLIT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) current;
acpi_create_slit(slit);
current += slit->header.length;
acpi_add_table(rsdp, slit);
/* SSDT */
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)current;
memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
current += ssdt->length;
memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
update_ssdt((void*)ssdt);
/* recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
acpi_add_table(rsdp,ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
current = acpi_add_ssdt_pstates(rsdp, current);
#if CONFIG_ACPI_SSDTX_NUM >= 1
/* same htio, but different position? We may have to copy,
change HCIN, and recalculate the checknum and add_table */
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
if((sysconf.pci1234[i] & 1) != 1 ) continue;
u8 c;
if (i < 7) {
c = (u8) ('4' + i - 1);
} else {
c = (u8) ('A' + i - 1 - 6);
}
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
ssdtx = (acpi_header_t *)current;
switch (sysconf.hcid[i]) {
case 1:
p = &AmlCode_ssdt2;
break;
case 2:
p = &AmlCode_ssdt3;
break;
case 3: /* 8131 */
p = &AmlCode_ssdt4;
break;
default:
/* HTX no io apic */
p = &AmlCode_ssdt5;
break;
}
memcpy(ssdtx, p, sizeof(acpi_header_t));
current += ssdtx->length;
memcpy(ssdtx, p, ssdtx->length);
update_ssdtx((void *)ssdtx, i);
ssdtx->checksum = 0;
ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
acpi_add_table(rsdp, ssdtx);
}
#endif
/* DSDT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current; // it will used by fadt
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current; // it will be used by fadt
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* FADT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
acpi_header_t *ssdt2;
acpi_header_t *alib;
acpi_hest_t *hest;
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */
start = ALIGN(start, 16);
current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt);
/* DSDT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current;
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* FADT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
/*
* We explicitly add these tables later on:
*/
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdp, madt);
/* HEST */
current = ALIGN(current, 8);
hest = (acpi_hest_t *)current;
acpi_write_hest((void *)current);
acpi_add_table(rsdp, (void *)current);
current += ((acpi_header_t *)current)->length;
/* SRAT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
if (srat != NULL) {
memcpy((void *)current, srat, srat->header.length);
srat = (acpi_srat_t *) current;
current += srat->header.length;
acpi_add_table(rsdp, srat);
}
else {
printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
}
/* SLIT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
if (slit != NULL) {
memcpy((void *)current, slit, slit->header.length);
slit = (acpi_slit_t *) current;
current += slit->header.length;
acpi_add_table(rsdp, slit);
}
else {
printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
}
/* SSDT */
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
if (alib != NULL) {
memcpy((void *)current, alib, alib->length);
alib = (acpi_header_t *) current;
current += alib->length;
acpi_add_table(rsdp, (void *)alib);
} else {
printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
}
/* The DSDT needs additional work for the AGESA SSDT Pstate table */
/* Keep the comment for a while. */
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) {
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
current += ssdt->length;
acpi_add_table(rsdp,ssdt);
} else {
printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n");
}
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current);
ssdt2 = (acpi_header_t *) current;
acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
current += ssdt2->length;
acpi_add_table(rsdp,ssdt2);
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
acpi_header_t *ssdtx;
void *p;
int i;
get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
/* Align ACPI tables to 16 bytes */
start = ( start + 0x0f) & -0x10;
current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt);
/* FACS */
printk(BIOS_DEBUG, "ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* DSDT */
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current;
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length);
/* FADT */
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
/*
* We explicitly add these tables later on:
*/
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n", current);
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current+=madt->header.length;
acpi_add_table(rsdp, madt);
/* SRAT */
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) current;
acpi_create_srat(srat);
current+=srat->header.length;
acpi_add_table(rsdp, srat);
/* SLIT */
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) current;
acpi_create_slit(slit);
current+=slit->header.length;
acpi_add_table(rsdp, slit);
/* SSDT */
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)current;
acpi_create_ssdt_generator(ssdt, "DYNADATA");
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
#if CONFIG_ACPI_SSDTX_NUM >= 1
//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
if((sysconf.pci1234[i] & 1) != 1 ) continue;
u8 c;
if(i<7) {
c = (u8) ('4' + i - 1);
}
else {
c = (u8) ('A' + i - 1 - 6);
}
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
ssdtx = (acpi_header_t *)current;
switch(sysconf.hcid[i]) {
case 1: //8132
p = &AmlCode_ssdt2;
break;
case 2: //8151
p = &AmlCode_ssdt3;
break;
case 3: //8131
p = &AmlCode_ssdt4;
break;
default:
continue;
}
memcpy(ssdtx, p, sizeof(acpi_header_t));
current += ssdtx->length;
memcpy(ssdtx, p, ssdtx->length);
update_ssdtx((void *)ssdtx, i);
ssdtx->checksum = 0;
ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
acpi_add_table(rsdp, ssdtx);
}
#endif
#if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length);
printk(BIOS_DEBUG, "srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length);
printk(BIOS_DEBUG, "slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length);
printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";
static const char productid[12] = "K9ND MS-9652";
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
int i,j;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
m = sysconf.mb;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(j= 0; j < 256 ; j++) {
if(m->bus_type[j])
smp_write_bus(mc, j, "PCI ");
}
smp_write_bus(mc, m->bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
}
dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword);
dword = 0x81001a00;
pci_write_config32(dev, 0x80, dword);
dword = 0xd00012d2;
pci_write_config32(dev, 0x84, dword);
}
}
mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
for(j=7; j>=2; j--) {
if(!m->bus_mcp55[j]) continue;
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
}
}
for(j=0; j<1; j++)
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
unsigned slot_num;
uint8_t *v;
unsigned sbdn;
uint8_t sum=0;
int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
/* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_ck804_0;
pirq->rtr_devfn = ((sbdn+9)<<3)|0;
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x10de;
pirq->rtr_device = 0x005c;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *) ( &pirq->checksum + 1);
slot_num = 0;
//pci bridge
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
//pcix bridge
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
//co processor
if(sysconf.pci1234[2] & 1) {
write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
}
#if 0
//smbus
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++;
//usb
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++;
//audio
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++;
//sata
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++;
//sata
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++;
//nic
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++;
//Slot1 PCIE x16
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
pirq_info++; slot_num++;
//firewire
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++;
//Slot2 pci
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
pirq_info++; slot_num++;
//Slot3 PCIE x16
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
pirq_info++; slot_num++;
//Slot4 PCIX
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
pirq_info++; slot_num++;
//Slot5 PCIX
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
pirq_info++; slot_num++;
//Slot6 PCIX
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
pirq_info++; slot_num++;
#endif
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum) {
pirq->checksum = sum;
}
printk(BIOS_INFO, "done.\n");
return (unsigned long) pirq_info;
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
struct resource *res;
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
res2mmio(res, 0, 0));
}
/* Initialize interrupt mapping. */
/*
LPC bridge PCI config registers:
0x7c:0x0000ffff
- bitmap of masked pci irqs?
- PIRQ[ABCD] possibly?
0x7c:0x00f00000
- sata at f8 - port 1
0x7c:0x0f000000
- sata at f7 - port 1
0x80:0xf0000000
- sata at f7 - port 0
0x80:0x0f000000
- sata at f8 - port 0
0x80:0x0000f000
- EHCI
0x84:0x00000f00
- NIC
0x84:0x0000000f
- OHCI
known values of nibbles:
0 - unrouted?
1 - irq 23
8 - irq 20
c - irq 12
d - irq 21
e - irq 14
f - irq 15
*/
// Enable interrupts for commonly used devices (USB, SATA, etc.)
pci_write_config32(dev, 0x7c, 0x0d800018);
pci_write_config32(dev, 0x80, 0xd8002009);
pci_write_config32(dev, 0x84, 0x00000001);
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
// Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
0xa);
// Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
0x15);
// Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
0x14);
// Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
0x17);
// Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
0x16);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, bus_ck804[0]);
/* There is no extension information... */
/* Compute the checksums. */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";
static const char productid[12] = "PA78VM5 ";
struct mp_config_table *mc;
int j;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
get_bus_conf();
/* Bus: Bus ID Type */
/* define bus and isa numbers */
for (j = 0; j < bus_isa; j++) {
smp_write_bus(mc, j, (char *)"PCI ");
}
smp_write_bus(mc, bus_isa, (char *)"ISA ");
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
u32 dword;
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
/* Initialize interrupt mapping */
/* aza */
byte = pci_read_config8(dev, 0x63);
byte &= 0xf8;
byte |= 0; /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";
static const char productid[12] = "TREX ";
struct mp_config_table *mc;
struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
get_bus_conf();
m = sysconf.mb;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
#if 0
unsigned char bus_num;
for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
printk(BIOS_DEBUG, "writing bus %d as PCI...\n",bus_num);
}
#endif
smp_write_bus(mc, 0, "PCI ");
smp_write_bus(mc, 1, "PCI ");
smp_write_bus(mc, 7, "PCI ");
smp_write_bus(mc, 8, "PCI ");
smp_write_bus(mc,m->bus_isa, "ISA ");
printk(BIOS_DEBUG, "writing %d as ISA...\n",m->bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev = 0;
int i;
struct resource *res;
for(i=0; i<3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base);
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
}
}
}
}
/* IRQ routing as factory BIOS */
outb(0x01, 0xc00); outb(0x0A, 0xc01);
outb(0x17, 0xc00); outb(0x05, 0xc01);
/* outb(0x2E, 0xc00); outb(0x0B, 0xc01); */
/* outb(0x07, 0xc00); outb(0x07, 0xc01); */
outb(0x07, 0xc00); outb(0x0b, 0xc01);
outb(0x24, 0xc00); outb(0x05, 0xc01);
//outb(0x00, 0xc00); outb(0x09, 0xc01);
outb(0x02, 0xc00); outb(0x0E, 0xc01);
// 8259 registers...
outb(0xa0, 0x4d0);
outb(0x0e, 0x4d1);
{
device_t dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
pci_write_config32(dev, 0x64, dword);
}
// set GEVENT pins to NO OP
outb(0x33, 0xcd6); outb(0x00, 0xcd7);
outb(0x34, 0xcd6); outb(0x00, 0xcd7);
outb(0x35, 0xcd6); outb(0x00, 0xcd7);
}
// hide XIOAPIC PCI configuration space
{
device_t dev;
dev = dev_find_device(0x1166, 0x205, 0);
if (dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
dword |= (1<<26);
pci_write_config32(dev, 0x64, dword);
}
}
mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_bcm5785[0], 0);
//SATA
/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
//USB
printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa);
//VGA
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7);
//PCIE
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe);
//IDE
// outb(0x02, 0xc00); outb(0x0e, 0xc01);
// printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe);
//onboard Broadcom GbE
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4);
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
{
device_t dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
dword |= (1<<4); // enable interrupts
printk(BIOS_DEBUG, "6ch: %x\n",dword);
pci_write_config32(dev, 0x6c, dword);
}
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
printk(BIOS_DEBUG, "m->bus_isa is: %x\n",m->bus_isa);
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1);
//extended table entries
smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0);
smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f);
smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006);
smp_write_bus_hierarchy(mc, 9, 0x01, 0);
smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16byte */
start = (start + 0x0f) & -0x10;
current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt);
/* FACS */
printk(BIOS_DEBUG, "ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* DSDT */
printk(BIOS_DEBUG, "ACPI: * DSDT\n");
dsdt = (acpi_header_t *)current;
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length);
/* FADT */
printk(BIOS_DEBUG, "ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
/*
* We explicitly add these tables later on:
*/
/* If we want to use HPET Timers Linux wants an MADT */
printk(BIOS_DEBUG, "ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet);
printk(BIOS_DEBUG, "ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdp, madt);
/* SSDT */
printk(BIOS_DEBUG, "ACPI: * SSDT\n");
ssdt = (acpi_header_t *)current;
acpi_create_ssdt_generator(ssdt, "DYNADATA");
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
#if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length);
printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
}
/* Initialize interrupt mapping*/
dword = 0x0120d218;
pci_write_config32(dev, 0x7c, dword);
dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d;
pci_write_config32(dev, 0x84, dword);
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
// Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
// Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
// Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
// Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
// Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
//Slot PCIE x16
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
}
//Slot PCIE x4
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
}
//Onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19
//Channel B of 8131
//Onboard Broadcom NIC
for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
}
//Channel A of 8131
//Slot 4 PCIX 133/100/66
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24
}
//Slot 3 PCIX 133/100/66 SoDIMM PCI
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
u32 dword;
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700,
0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
byte = pci_read_config8(dev, 0x63);
byte &= 0xf8;
byte |= 0; /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
u32 dword;
u8 byte;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
get_bus_conf();
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);
apicid_hudson = IO_APIC_ID;
smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
int boot_apic_id;
unsigned apic_version;
unsigned cpu_features;
unsigned cpu_feature_flags;
struct cpuid_result result;
unsigned long cpu_flag;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
/*Inagua used dure core cpu with one die */
boot_apic_id = lapicid();
apic_version = lapic_read(LAPIC_LVR) & 0xff;
result = cpuid(1);
cpu_features = result.eax;
cpu_feature_flags = result.edx;
cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
smp_write_processor(mc,
0, apic_version,
cpu_flag, cpu_features, cpu_feature_flags
);
cpu_flag = MPC_CPU_ENABLED;
smp_write_processor(mc,
1, apic_version,
cpu_flag, cpu_features, cpu_feature_flags
);
get_bus_conf();
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
device_t dev;
u32 dword;
u8 byte;
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);
apicid_sb900 = IO_APIC_ID;
smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
//mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0);
/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1);
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb900, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sb900, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sb900, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, 0x49, apicid_sb900, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sb900, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sb900, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sb900, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_sb900, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0xa, apicid_sb900, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0x1c, apicid_sb900, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sb900, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sb900, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sb900, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sb900, 0xf);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb900[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb900[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb900[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb900[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb900[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb900[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb900[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb900[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb900[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15);
PCI_INT(bus_sb900[2], 0x0, 0x0, 0x12);
PCI_INT(bus_sb900[2], 0x0, 0x1, 0x13);
PCI_INT(bus_sb900[2], 0x0, 0x2, 0x14);
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
acpi_header_t *alib;
acpi_header_t *ivrs;
acpi_hest_t *hest;
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */
start = ALIGN(start, 16);
current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt);
/* DSDT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current; /* it will used by fadt */
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ /* it needs 64 bit alignment */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current; /* it will be used by fadt */
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* FADT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
/*
* We explicitly add these tables later on:
*/
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdp, madt);
/* HEST */
current = ALIGN(current, 8);
hest = (acpi_hest_t *)current;
acpi_write_hest((void *)current);
acpi_add_table(rsdp, (void *)current);
current += ((acpi_header_t *)current)->length;
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
if (ivrs != NULL) {
memcpy((void *)current, ivrs, ivrs->length);
ivrs = (acpi_header_t *) current;
current += ivrs->length;
acpi_add_table(rsdp, ivrs);
} else {
printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
}
/* SRAT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
if (srat != NULL) {
memcpy((void *)current, srat, srat->header.length);
srat = (acpi_srat_t *) current;
current += srat->header.length;
acpi_add_table(rsdp, srat);
} else {
printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
}
/* SLIT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
if (slit != NULL) {
memcpy((void *)current, slit, slit->header.length);
slit = (acpi_slit_t *) current;
current += slit->header.length;
acpi_add_table(rsdp, slit);
} else {
printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
}
/* ALIB */
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
if (alib != NULL) {
memcpy((void *)current, alib, alib->length);
alib = (acpi_header_t *) current;
current += alib->length;
acpi_add_table(rsdp, (void *)alib);
}
else {
printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
}
/* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */
/* SSDT */
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) {
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
current += ssdt->length;
}
else {
printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
}
acpi_add_table(rsdp,ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
printk(BIOS_DEBUG, "ACPI: * SSDT\n");
ssdt = (acpi_header_t *)current;
acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
#if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length);
printk(BIOS_DEBUG, "srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length);
printk(BIOS_DEBUG, "slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length);
printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
printk(BIOS_DEBUG, "hest\n");
dump_mem(hest, ((void *)hest) + hest->header.length);
#endif
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
unsigned slot_num;
uint8_t *v;
struct mb_sysconf_t *m;
unsigned sbdn;
uint8_t sum=0;
int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn;
m = sysconf.mb;
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
/* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = m->bus_mcp55;
pirq->rtr_devfn = ((sbdn+6)<<3)|0;
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x10de;
pirq->rtr_device = 0x0370;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *) ( &pirq->checksum + 1);
slot_num = 0;
//pci bridge
write_pirq_info(pirq_info, m->bus_mcp55, ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
for (i = 1; i < sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff;
write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
}
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum) {
pirq->checksum = sum;
}
printk(BIOS_INFO, "done.\n");
return (unsigned long) pirq_info;
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
//
// The commented-out lines are auto-detected on my servers.
//
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
// Integrated SMBus 2.0
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
// Integrated AMD AC97 Audio
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
// Integrated AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13);
// On board ATI Rage XL
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
// On board Broadcom nics
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
// On board LSI SCSI
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
// PCIX-133 Slot
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600);
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
struct resource *res;
res = find_resource(dev, 0x74);
smp_write_ioapic(mc, apicid_sb600, 0x20,
res2mmio(res, 0, 0));
}
}
mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0);
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
/* usb */
PCI_INT(0x0, 0x13, 0x0, 0x10);
PCI_INT(0x0, 0x13, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x2, 0x12);
PCI_INT(0x0, 0x13, 0x3, 0x13);
/* sata */
PCI_INT(0x0, 0x12, 0x1, 0x16);
/* SMBus/ACPI */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* IDE */
PCI_INT(0x0, 0x14, 0x1, 0x11);
/* HDA */
PCI_INT(0x0, 0x14, 0x2, 0x12);
/* LPC */
PCI_INT(0x0, 0x14, 0x3, 0x13);
/* GFX ? */
PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
/* PCIe slots */
PCI_INT(0x2, 0x00, 0x00, 0x10);
PCI_INT(0x2, 0x00, 0x01, 0x11);
PCI_INT(0x2, 0x00, 0x02, 0x12);
PCI_INT(0x2, 0x00, 0x03, 0x13);
/* PCIe slots */
PCI_INT(0x3, 0x00, 0x00, 0x11);
PCI_INT(0x3, 0x00, 0x01, 0x12);
PCI_INT(0x3, 0x00, 0x02, 0x13);
PCI_INT(0x3, 0x00, 0x03, 0x10);
/* PCIe slots */
PCI_INT(0x4, 0x00, 0x00, 0x12);
PCI_INT(0x4, 0x00, 0x01, 0x13);
PCI_INT(0x4, 0x00, 0x02, 0x10);
PCI_INT(0x4, 0x00, 0x03, 0x11);
/* PCIe slots */
PCI_INT(0x5, 0x00, 0x00, 0x13);
PCI_INT(0x5, 0x00, 0x01, 0x10);
PCI_INT(0x5, 0x00, 0x02, 0x11);
PCI_INT(0x5, 0x00, 0x03, 0x12);
/* onboard NIC ? */
PCI_INT(bus_sb600[1], 0x7, 0x0, 0x13);
PCI_INT(bus_sb600[1], 0x7, 0x1, 0x10);
PCI_INT(bus_sb600[1], 0x7, 0x2, 0x11);
PCI_INT(bus_sb600[1], 0x7, 0x3, 0x12);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);
/* Compute the checksums */
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
m = sysconf.mb;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
}
dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword);
dword = 0x81001a00;
pci_write_config32(dev, 0x80, dword);
dword = 0xd00012d2;
pci_write_config32(dev, 0x84, dword);
}
}
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
for(j=7; j>=2; j--) {
if(!m->bus_mcp55[j]) continue;
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
}
}
for(j=0; j<1; j++)
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
unsigned slot_num;
uint8_t *v;
uint8_t sum=0;
int i;
struct mb_sysconf_t *m;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
m = sysconf.mb;
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
/* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = m->bus_8111_0;
pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x1022;
pirq->rtr_device = 0x746b;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *) ( &pirq->checksum + 1);
slot_num = 0;
{
device_t dev;
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3));
if (dev) {
/* initialize PCI interupts - these assignments depend
on the PCB routing of PINTA-D
PINTA = IRQ3
PINTB = IRQ5
PINTC = IRQ10
PINTD = IRQ11
*/
pci_write_config16(dev, 0x56, 0xba53);
}
}
//pci bridge
printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n");
static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4);
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
printk(BIOS_DEBUG, "setting Onboard AMD USB\n");
static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11};
pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
//pcix bridge
// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++;
int j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff;
write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
j++;
}
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum) {
pirq->checksum = sum;
}
printk(BIOS_INFO, "done.\n");
return (unsigned long) pirq_info;
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int i, bus_isa;
struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
m = sysconf.mb;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev = 0;
struct resource *res;
for(i=0; i<3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
}
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
//IDE
outb(0x02, 0xc00); outb(0x0e, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE
//SATA
outb(0x07, 0xc00); outb(0x0f, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf);
//USB
outb(0x01, 0xc00); outb(0x0a, 0xc01);
for(i=0;i<3;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
}
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
{
device_t dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
dword |= (1<<4); // enable interrupts
pci_write_config32(dev, 0x6c, dword);
}
}
//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
// AIC 8130 Galileo Technology...
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
}
//pci slot (on bcm5785)
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); //
}
//onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
}
//onboard Broadcom
for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
}
// First PCI-E x8
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); //
}
// Second PCI-E x8
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); //
}
// Third PCI-E x1
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); //
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
u32 dword;
u8 byte;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_ioread(0x34) & 0xF0;
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
u32 slot_num;
u8 *v;
u8 sum = 0;
int i;
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
/* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (u8 *) (addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb800[0];
pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x1002;
pirq->rtr_device = 0x4384;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;
slot_num++;
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum) {
pirq->checksum = sum;
}
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
return (unsigned long)pirq_info;
}
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
unsigned slot_num;
uint8_t *v;
unsigned sbdn;
uint8_t sum=0;
int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
/* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = 0;
pirq->rtr_devfn = PCI_DEVFN(2, 0);
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = PCI_VENDOR_ID_SIS;
pirq->rtr_device = PCI_DEVICE_ID_SIS_SIS966_LPC;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *) ( &pirq->checksum + 1);
slot_num = 0;
write_pirq_info(pirq_info, 0, PCI_DEVFN(2, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum) {
pirq->checksum = sum;
}
printk(BIOS_INFO, "done.\n");
{
device_t dev;
dev = dev_find_slot(0, PCI_DEVFN(2,0));
if (dev) {
/* initialize PCI interupts - these assignments depend
on the PCB routing of PINTA-D
PINTA = IRQ10
PINTB = IRQ11
PINTC = NA
PINTD = IRQ10
PINTE = IRQ11
PINTF = IRQ5
PINTG = NA
PINTH = IRQ7
*/
uint8_t reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63};
uint8_t irq[8]={0x0A,0X0B,0X0,0X0a,0X0B,0X05,0X0,0X07};
for(i=0;i<8;i++)
pci_write_config8(dev, reg[i], irq[i]);
} // endif
printk(BIOS_DEBUG, "Setting Onboard SiS Southbridge\n");
dev = dev_find_slot(0, PCI_DEVFN(2,5)); // 5513 (IDE)
pci_write_config8(dev, 0x3C, 0x0A);
dev = dev_find_slot(0, PCI_DEVFN(3,0)); // USB 1.1
pci_write_config8(dev, 0x3C, 0x0B);
dev = dev_find_slot(0, PCI_DEVFN(3,1)); // USB 1.1
pci_write_config8(dev, 0x3C, 0x05);
dev = dev_find_slot(0, PCI_DEVFN(3,3)); // USB 2.0
pci_write_config8(dev, 0x3C, 0x07);
dev = dev_find_slot(0, PCI_DEVFN(4,0)); // 191 (LAN)
pci_write_config8(dev, 0x3C, 0x0A);
dev = dev_find_slot(0, PCI_DEVFN(5,0)); // 1183 (SATA)
pci_write_config8(dev, 0x3C, 0x0B);
dev = dev_find_slot(0, PCI_DEVFN(6,0)); // PCI-E
pci_write_config8(dev, 0x3C, 0x0A);
dev = dev_find_slot(0, PCI_DEVFN(7,0)); // PCI-E
pci_write_config8(dev, 0x3C, 0x0A);
dev = dev_find_slot(0, PCI_DEVFN(15,0)); // Azalia
pci_write_config8(dev, 0x3C, 0x05);
}
printk(BIOS_DEBUG, "pirq routing table, size=%d\n", pirq->size);
for (i = 0; i < pirq->size; i+=4)
printk(BIOS_DEBUG, "%.2x%.2x%.2x%.2x\n", v[i+3],v[i+2],v[i+1],v[i]);
return (unsigned long) pirq_info;
}
