static void imx_ssi_timer_callback(unsigned long data) { struct snd_pcm_substream *substream = (void *)data; struct snd_pcm_runtime *runtime = substream->runtime; struct imx_pcm_runtime_data *iprtd = runtime->private_data; struct pt_regs regs; unsigned long delta; get_fiq_regs(®s); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) iprtd->offset = regs.ARM_r8 & 0xffff; else iprtd->offset = regs.ARM_r9 & 0xffff; /* How much data have we transferred since the last period report? */ if (iprtd->offset >= iprtd->last_offset) delta = iprtd->offset - iprtd->last_offset; else delta = runtime->buffer_size + iprtd->offset - iprtd->last_offset; /* If we've transferred at least a period then report it and * reset our poll time */ if (delta >= runtime->period_size) { snd_pcm_period_elapsed(substream); iprtd->last_offset = iprtd->offset; imx_ssi_set_next_poll(iprtd); } /* Restart the timer; if we didn't report we'll run on the next tick */ add_timer(&iprtd->timer); }
void __init init_FIQ(int start) { unsigned offset = FIQ_OFFSET; dfl_fiq_insn = *(unsigned long *)(0xffff0000 + offset); get_fiq_regs(&dfl_fiq_regs); fiq_start = start; }
static int snd_imx_pcm_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct imx_pcm_runtime_data *iprtd = runtime->private_data; struct pt_regs regs; get_fiq_regs(®s); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) regs.ARM_r8 = (iprtd->period * iprtd->periods - 1) << 16; else regs.ARM_r9 = (iprtd->period * iprtd->periods - 1) << 16; set_fiq_regs(®s); return 0; }
static int floppy_get_residue(dmach_t channel, dma_t *dma) { struct pt_regs regs; get_fiq_regs(®s); return regs.ARM_r9; }
static int __init stmp3xxx_bat_init(void) { #ifdef POWER_FIQ int ret; ret = claim_fiq(&power_fiq); if (ret) { pr_err("Can't claim fiq"); } else { get_fiq_regs(&fiq_regs); set_fiq_handler(power_fiq_start, power_fiq_end-power_fiq_start); lock_vector_tlb((void *)0xffff0000); lock_vector_tlb(REGS_POWER_BASE); /* disable interrupts to be configured as FIQs */ __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, HW_ICOLL_INTERRUPTn_CLR_ADDR(IRQ_DCDC4P2_BO)); __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, HW_ICOLL_INTERRUPTn_CLR_ADDR(IRQ_BATT_BRNOUT)); __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, HW_ICOLL_INTERRUPTn_CLR_ADDR(IRQ_VDDD_BRNOUT)); __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, HW_ICOLL_INTERRUPTn_CLR_ADDR(IRQ_VDD18_BRNOUT)); __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, HW_ICOLL_INTERRUPTn_CLR_ADDR(IRQ_VDD5V_DROOP)); /* Enable these interrupts as FIQs */ __raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ, HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_DCDC4P2_BO)); __raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ, HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_BATT_BRNOUT)); __raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ, HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDDD_BRNOUT)); __raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ, HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDD18_BRNOUT)); __raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ, HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDD5V_DROOP)); /* enable FIQ functionality */ __raw_writel(BM_ICOLL_CTRL_FIQ_FINAL_ENABLE, HW_ICOLL_CTRL_SET_ADDR); /* enable these interrupts */ __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_DCDC4P2_BO)); __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_BATT_BRNOUT)); __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDDD_BRNOUT)); __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDD18_BRNOUT)); __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, HW_ICOLL_INTERRUPTn_SET_ADDR(IRQ_VDD5V_DROOP)); } #endif return platform_driver_register(&stmp3xxx_batdrv); }