static int exynos5_init_isp_table(struct device *dev, struct devfreq_data_isp *data)
{
unsigned int i;
unsigned int ret;
unsigned int freq;
unsigned int volt;
for (i = 0; i < data->max_state; ++i) {
freq = devfreq_isp_opp_list[i].freq;
volt = get_match_volt(ID_ISP, freq);
if (!volt)
volt = devfreq_isp_opp_list[i].volt;
exynos5_devfreq_isp_profile.freq_table[i] = freq;
ret = opp_add(dev, freq, volt);
if (ret) {
pr_err("DEVFREQ(ISP) : Failed to add opp entries %uKhz, %uV\n", freq, volt);
return ret;
} else {
pr_info("DEVFREQ(ISP) : %uKhz, %uV\n", freq, volt);
}
}
return 0;
}
static int exynos7_init_disp_table(struct device *dev, struct devfreq_data_disp *data)
{
unsigned int i;
unsigned int ret;
unsigned int freq;
unsigned int volt;
for (i = 0; i < data->max_state; ++i) {
freq = devfreq_disp_opp_list[i].freq;
volt = get_match_volt(ID_ISP, freq);
if (!volt)
volt = devfreq_disp_opp_list[i].volt;
devfreq_disp_opp_list[i].volt = volt;
exynos7_devfreq_disp_profile.freq_table[i] = freq;
ret = opp_add(dev, freq, volt);
if (ret) {
pr_err("DEVFREQ(DISP) : Failed to add opp entries %uKhz, %uuV\n", freq, volt);
return ret;
} else {
pr_info("DEVFREQ(DISP) : %7uKhz, %7uuV\n", freq, volt);
}
}
opp_disable(dev, devfreq_disp_opp_list[0].freq);
opp_disable(dev, devfreq_disp_opp_list[1].freq);
data->volt_of_avail_max_freq = get_volt_of_avail_max_freq(dev);
pr_info("DEVFREQ(DISP) : voltage of available max freq : %7uuV\n",
data->volt_of_avail_max_freq);
return 0;
}
static int exynos5_init_int_table(struct device *dev,
struct devfreq_data_int *data)
{
unsigned int i;
unsigned int ret;
unsigned int freq;
unsigned int volt;
exynos5_devfreq_int_profile.max_state = data->max_state;
data->int_asv_abb_table = kzalloc(sizeof(int) * data->max_state, GFP_KERNEL);
for (i = 0; i < data->max_state; ++i) {
freq = devfreq_int_opp_list[i].freq;
volt = get_match_volt(ID_INT, freq);
if (!volt)
volt = devfreq_int_opp_list[i].volt;
exynos5_devfreq_int_profile.freq_table[i] = freq;
devfreq_int_opp_list[i].volt = volt;
ret = opp_add(dev, freq, volt);
if (ret) {
pr_err("DEVFREQ(INT) : Failed to add opp entries %uKhz, %uV\n", freq, volt);
return ret;
} else {
pr_info("DEVFREQ(INT) : %uKhz, %uV\n", freq, volt);
}
data->int_asv_abb_table[i] = get_match_abb(ID_INT, freq);
pr_info("DEVFREQ(INT) : %uKhz, ABB %u\n", freq, data->int_asv_abb_table[i]);
}
return 0;
}
int gpu_regulator_init(struct exynos_context *platform)
{
int gpu_voltage = 0;
g3d_regulator = regulator_get(NULL, "vdd_g3d");
if (IS_ERR(g3d_regulator)) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to get vdd_g3d regulator, 0x%p\n", __func__, g3d_regulator);
g3d_regulator = NULL;
return -1;
}
gpu_voltage = get_match_volt(ID_G3D, platform->gpu_dvfs_config_clock*1000);
if (gpu_voltage == 0)
gpu_voltage = platform->gpu_default_vol;
if (gpu_set_voltage(platform, gpu_voltage) != 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to set voltage [%d]\n", __func__, gpu_voltage);
return -1;
}
if (platform->dvs_status)
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "dvs GPIO PMU status enable\n");
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "regulator initialized\n");
return 0;
}
int kbase_platform_regulator_init(void)
{
#ifdef CONFIG_REGULATOR
int mali_gpu_vol = 0;
g3d_regulator = regulator_get(NULL, "vdd_g3d");
if (IS_ERR(g3d_regulator)) {
printk("[kbase_platform_regulator_init] failed to get mali t6xx regulator, 0x%p\n", g3d_regulator);
g3d_regulator = NULL;
return -1;
}
if (regulator_enable(g3d_regulator) != 0) {
printk("[kbase_platform_regulator_init] failed to enable mali t6xx regulator\n");
g3d_regulator = NULL;
return -1;
}
#ifdef MALI_DVFS_ASV_ENABLE
mali_gpu_vol = get_match_volt(ID_G3D, MALI_DVFS_BL_CONFIG_FREQ*1000);
#endif
if (mali_gpu_vol == 0)
mali_gpu_vol = mali_dvfs_infotbl[ARRAY_SIZE(mali_dvfs_infotbl)-1].voltage;
if (regulator_set_voltage(g3d_regulator, mali_gpu_vol, mali_gpu_vol) != 0) {
printk("[kbase_platform_regulator_init] failed to set mali t6xx operating voltage [%d]\n", mali_gpu_vol);
return -1;
}
#endif
return 0;
}
static int mali_dvfs_update_asv(int cmd)
{
int i;
int voltage = 0;
if (cmd == ASV_CMD_DISABLE) {
for (i = 0; i < MALI_DVFS_STEP; i++) {
mali_dvfs_infotbl[i].voltage = mali_dvfs_vol_default[i];
}
printk("mali_dvfs_update_asv use default table\n");
return ASV_STATUS_INIT;
}
for (i = 0; i < MALI_DVFS_STEP; i++) {
voltage = get_match_volt(ID_G3D, mali_dvfs_infotbl[i].clock*1000);
if (voltage == 0) {
return ASV_STATUS_NOT_INIT;
}
printk(KERN_INFO "G3D %dKhz ASV is %duV\n",
mali_dvfs_infotbl[i].clock*1000, voltage);
mali_dvfs_infotbl[i].voltage = voltage;
}
return ASV_STATUS_INIT;
}
static void __init set_volt_table_CA53(void)
{
unsigned int i;
unsigned int asv_volt = 0;
for (i = 0; i < CPUFREQ_LEVEL_END_CA53; i++) {
asv_volt = get_match_volt(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
if (!asv_volt)
exynos7420_volt_table_CA53[i] = asv_voltage_7420_CA53[i];
else
exynos7420_volt_table_CA53[i] = asv_volt;
pr_info("CPUFREQ of CA53 L%d : %d uV\n", i,
exynos7420_volt_table_CA53[i]);
exynos7420_abb_table_CA53[i] =
get_match_abb(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
pr_info("CPUFREQ of CA53 L%d : ABB %d\n", i,
exynos7420_abb_table_CA53[i]);
}
switch (exynos_get_table_ver()) {
case 0 :
case 1 :
case 4 :
max_support_idx_CA53 = L6; break; /* 1.4GHz */
case 5 :
max_support_idx_CA53 = L8; break; /* 1.2GHz */
default :
#ifdef CONFIG_AP_FIVE
max_support_idx_CA53 = L5; /* 1.5GHz */
#else
#ifdef CONFIG_AP_SIX
max_support_idx_CA53 = L4; /* 1.6GHz */
#else
#ifdef CONFIG_AP_SEVEN
max_support_idx_CA53 = L3; /* 1.7GHz */
#endif
#endif
#endif
}
#ifdef CONFIG_AP_MIN_FOUR
min_support_idx_CA53 = L16; /* 400MHz */
#else
#ifdef CONFIG_AP_MIN_TWO
min_support_idx_CA53 = L18; /* 200MHz */
#endif
#endif
pr_info("CPUFREQ of CA53 max_freq : L%d %u khz\n", max_support_idx_CA53,
exynos7420_freq_table_CA53[max_support_idx_CA53].frequency);
pr_info("CPUFREQ of CA53 min_freq : L%d %u khz\n", min_support_idx_CA53,
exynos7420_freq_table_CA53[min_support_idx_CA53].frequency);
}
int gpu_regulator_init(struct exynos_context *platform)
{
int gpu_voltage = 0;
g3d_regulator = regulator_get(NULL, "vdd_g3d");
if (IS_ERR(g3d_regulator)) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to get vdd_g3d regulator, 0x%p\n", __func__, g3d_regulator);
g3d_regulator = NULL;
return -1;
}
if (platform->dvs_status) {
dvs_en_regulator = regulator_get(NULL, "DVS_EN");
if (IS_ERR(dvs_en_regulator)) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to get DVS_EN regulator, 0x%p\n", __func__, dvs_en_regulator);
dvs_en_regulator = NULL;
return -1;
}
if (gpu_enable_dvs_en_regulator(platform) != 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to enable dvs_en regulator\n", __func__);
dvs_en_regulator = NULL;
return -1;
}
if (gpu_disable_dvs_en_regulator(platform) != 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to disable dvs_en regulator\n", __func__);
dvs_en_regulator = NULL;
return -1;
}
platform->dvs_is_enabled = false;
}
gpu_voltage = get_match_volt(ID_G3D, platform->gpu_dvfs_config_clock*1000);
if (gpu_voltage == 0)
gpu_voltage = platform->gpu_default_vol;
if (gpu_set_voltage(platform, gpu_voltage) != 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to set voltage [%d]\n", __func__, gpu_voltage);
return -1;
}
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "regulator initialized\n");
return 0;
}
static void __init set_volt_table_CA57(void)
{
unsigned int i;
unsigned int asv_volt = 0;
for (i = 0; i < CPUFREQ_LEVEL_END_CA57; i++) {
asv_volt = get_match_volt(ID_CL1, exynos7420_freq_table_CA57[i].frequency);
if (!asv_volt)
exynos7420_volt_table_CA57[i] = asv_voltage_7420_CA57[i];
else
exynos7420_volt_table_CA57[i] = asv_volt;
pr_info("CPUFREQ of CA57 L%d : %d uV\n", i,
exynos7420_volt_table_CA57[i]);
exynos7420_abb_table_CA57[i] =
get_match_abb(ID_CL1, exynos7420_freq_table_CA57[i].frequency);
pr_info("CPUFREQ of CA57 L%d : ABB %d\n", i,
exynos7420_abb_table_CA57[i]);
}
#if defined(CONFIG_CPU_THERMAL) && defined(CONFIG_EXYNOS5_DYNAMIC_CPU_HOTPLUG)
switch (exynos_get_table_ver()) {
case 0 :
case 1 :
case 4 :
max_support_idx_CA57 = L7; break; /* 1.8GHz */
case 5 :
max_support_idx_CA57 = L10; break; /* 1.5GHz */
default :
max_support_idx_CA57 = L4; /* 2.1GHz */
}
#else
max_support_idx_CA57 = L13; /* 1.2 GHz */
#endif
#ifdef CONFIG_S6_LOW_IDLE
min_support_idx_CA57 = L21; /* 400 MHz */
#else
min_support_idx_CA57 = L17; /* 800 MHz */
#endif
pr_info("CPUFREQ of CA57 max_freq : L%d %u khz\n", max_support_idx_CA57,
exynos7420_freq_table_CA57[max_support_idx_CA57].frequency);
pr_info("CPUFREQ of CA57 min_freq : L%d %u khz\n", min_support_idx_CA57,
exynos7420_freq_table_CA57[min_support_idx_CA57].frequency);
}
static int gpu_dvfs_update_asv_table(struct exynos_context *platform)
{
int i, voltage, dvfs_table_size;
gpu_dvfs_info *dvfs_table;
#ifdef CONFIG_PWRCAL
struct dvfs_rate_volt g3d_rate_volt[48];
int cal_table_size;
int j;
dvfs_table = platform->table;
dvfs_table_size = platform->table_size;
cal_table_size = cal_dfs_get_rate_asv_table(dvfs_g3d, g3d_rate_volt);
if (!cal_table_size)
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "Failed get G3D ASV table\n");
for (i = 0; i < dvfs_table_size; i++) {
for (j = 0; j < cal_table_size; j++) {
if (dvfs_table[i].clock * 1000 == g3d_rate_volt[j].rate) {
voltage = g3d_rate_volt[j].volt;
if (voltage > 0) {
dvfs_table[i].voltage = g3d_rate_volt[j].volt;
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "G3D %dKhz ASV is %duV\n", dvfs_table[i].clock*1000, dvfs_table[i].voltage);
}
}
}
}
#else
DVFS_ASSERT(platform);
dvfs_table = platform->table;
dvfs_table_size = platform->table_size;
for (i = 0; i < dvfs_table_size; i++) {
if (platform->dynamic_abb_status) {
dvfs_table[i].asv_abb = get_match_abb(ID_G3D, dvfs_table[i].clock*1000);
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "DEVFREQ: %uKhz, ABB %u\n", dvfs_table[i].clock*1000, dvfs_table[i].asv_abb);
}
voltage = get_match_volt(ID_G3D, dvfs_table[i].clock*1000);
if (voltage > 0)
dvfs_table[i].voltage = voltage;
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "G3D %dKhz ASV is %duV\n", dvfs_table[i].clock*1000, dvfs_table[i].voltage);
}
#endif
return 0;
}
void sec_gpu_dvfs_init(void)
{
struct platform_device *pdev;
int i = 0;
ssize_t total = 0, offset = 0;
memset(gdata, 0x00, sizeof(struct gpu_dvfs_data)*MAX_DVFS_LEVEL);
for (i = 0; i < GPU_DVFS_MAX_LEVEL; i++) {
gdata[i].level = default_dvfs_data[i].level;
gdata[i].clock = default_dvfs_data[i].clock;
gdata[i].voltage = get_match_volt(ID_G3D, default_dvfs_data[i].clock * 1000);
gdata[i].clock_source = default_dvfs_data[i].clock_source;
gdata[i].min_threadhold = default_dvfs_data[i].min_threadhold;
gdata[i].max_threadhold = default_dvfs_data[i].max_threadhold;
gdata[i].quick_down_threadhold = default_dvfs_data[i].quick_down_threadhold;
gdata[i].quick_up_threadhold = default_dvfs_data[i].quick_up_threadhold;
gdata[i].stay_total_count = default_dvfs_data[i].stay_total_count;
gdata[i].mask = setmask(default_dvfs_data[i].level, default_dvfs_data[i].clock);
PVR_LOG(("G3D DVFS Info: Level:%d, Clock:%d MHz, Voltage:%d uV", gdata[i].level, gdata[i].clock, gdata[i].voltage));
}
/* default dvfs level depend on default clock setting */
sgx_dvfs_level = sec_gpu_dvfs_level_from_clk_get(gpu_clock_get());
sgx_dvfs_down_requirement = DOWN_REQUIREMENT_THRESHOLD;
pdev = gpsPVRLDMDev;
/* Required name attribute */
if (device_create_file(&pdev->dev, &dev_attr_sgx_dvfs_min_lock) < 0)
PVR_LOG(("device_create_file: dev_attr_sgx_dvfs_min_lock fail"));
if (device_create_file(&pdev->dev, &dev_attr_sgx_dvfs_max_lock) < 0)
PVR_LOG(("device_create_file: dev_attr_sgx_dvfs_max_lock fail"));
if (device_create_file(&pdev->dev, &dev_attr_sgx_dvfs_volt_table) < 0)
PVR_LOG(("device_create_file: dev_attr_sgx_dvfs_volt_table fail"));
/* Generate DVFS table list*/
for( i = 0; i < GPU_DVFS_MAX_LEVEL ; i++) {
offset = sprintf(sgx_dvfs_table_string+total, "%d\n", gdata[i].clock);
total += offset;
}
sgx_dvfs_table = sgx_dvfs_table_string;
if (device_create_file(&pdev->dev, &dev_attr_sgx_dvfs_table) < 0)
PVR_LOG(("device_create_file: dev_attr_sgx_dvfs_table fail"));
}
static void __init set_volt_table_CA53(void)
{
unsigned int i;
unsigned int asv_volt = 0;
for (i = 0; i < CPUFREQ_LEVEL_END_CA53; i++) {
asv_volt = get_match_volt(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
if (!asv_volt)
exynos7420_volt_table_CA53[i] = asv_voltage_7420_CA53[i];
else
exynos7420_volt_table_CA53[i] = asv_volt;
pr_info("CPUFREQ of CA53 L%d : %d uV\n", i,
exynos7420_volt_table_CA53[i]);
exynos7420_abb_table_CA53[i] =
get_match_abb(ID_CL0, exynos7420_freq_table_CA53[i].frequency);
pr_info("CPUFREQ of CA53 L%d : ABB %d\n", i,
exynos7420_abb_table_CA53[i]);
}
switch (exynos_get_table_ver()) {
case 0 :
case 1 :
case 4 :
max_support_idx_CA53 = L6; break; /* 1.4GHz */
case 5 :
max_support_idx_CA53 = L8; break; /* 1.2GHz */
case 12 :
max_support_idx_CA53 = L7; break; /* 1.3GHz */
default :
max_support_idx_CA53 = EXYNOS7420_CPU_MAX_FREQ_LITTLE;
}
min_support_idx_CA53 = EXYNOS7420_CPU_MIN_FREQ_LITTLE;
pr_info("CPUFREQ of CA53 max_freq : L%d %u khz\n", max_support_idx_CA53,
exynos7420_freq_table_CA53[max_support_idx_CA53].frequency);
pr_info("CPUFREQ of CA53 min_freq : L%d %u khz\n", min_support_idx_CA53,
exynos7420_freq_table_CA53[min_support_idx_CA53].frequency);
}
static int gpu_dvfs_update_asv_table(struct exynos_context *platform)
{
int i, voltage, dvfs_table_size;
gpu_dvfs_info *dvfs_table;
DVFS_ASSERT(platform);
dvfs_table = platform->table;
dvfs_table_size = platform->table_size;
for (i = 0; i < dvfs_table_size; i++) {
if (platform->dynamic_abb_status) {
dvfs_table[i].asv_abb = get_match_abb(ID_G3D, dvfs_table[i].clock*1000);
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "DEVFREQ: %uKhz, ABB %u\n", dvfs_table[i].clock*1000, dvfs_table[i].asv_abb);
}
voltage = get_match_volt(ID_G3D, dvfs_table[i].clock*1000);
if (voltage > 0)
dvfs_table[i].voltage = voltage;
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "G3D %dKhz ASV is %duV\n", dvfs_table[i].clock*1000, dvfs_table[i].voltage);
}
return 0;
}
static int gpu_dvfs_update_asv_table(struct exynos_context *platform, int governor_type)
{
int i, voltage;
#if SOC_NAME == 5260
unsigned int asv_abb = 0;
#endif /* SOC_NAME */
for (i = 0; i < platform->table_size; i++) {
#if SOC_NAME == 5260
asv_abb = get_match_abb(ID_G3D, platform->table[i].clock*1000);
if (!asv_abb) {
platform->devfreq_g3d_asv_abb[i] = ABB_BYPASS;
} else {
platform->devfreq_g3d_asv_abb[i] = asv_abb;
}
GPU_LOG(DVFS_INFO, "DEVFREQ(G3D) : %uKhz, ABB %u\n", platform->table[i].clock*1000, platform->devfreq_g3d_asv_abb[i]);
#endif /* SOC_NAME */
voltage = get_match_volt(ID_G3D, platform->table[i].clock*1000);
if (voltage > 0)
platform->table[i].voltage = voltage;
GPU_LOG(DVFS_INFO, "G3D %dKhz ASV is %duV\n", platform->table[i].clock*1000, platform->table[i].voltage);
}
return 0;
}
int gpu_regulator_init(struct exynos_context *platform)
{
int gpu_voltage = 0;
#if 0
platform->g3d_regulator = regulator_get(NULL, "vdd_g3d");
#endif
if (IS_ERR(platform->g3d_regulator)) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to get regulator, 0x%p\n", __func__, platform->g3d_regulator);
platform->g3d_regulator = NULL;
return -1;
}
if (gpu_regulator_enable(platform) != 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to enable regulator\n", __func__);
platform->g3d_regulator = NULL;
return -1;
}
#if 0
gpu_voltage = get_match_volt(ID_G3D, platform->gpu_dvfs_config_clock*1000);
#else
gpu_voltage = 0;
#endif
if (gpu_voltage == 0)
gpu_voltage = platform->gpu_default_vol;
if (gpu_set_voltage(platform, gpu_voltage) != 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to set voltage [%d]\n", __func__, gpu_voltage);
return -1;
}
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "regulator initialized\n");
return 0;
}
static int mali_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
{
unsigned int nextStatus = (unsigned int)*freq;
unsigned int curStatus = 0;
curStatus = maliDvfsStatus.currentStep;
MALI_DEBUG_PRINT(4, ("= curStatus %d, nextStatus %d, maliDvfsStatus.currentStep %d\n", curStatus, nextStatus, maliDvfsStatus.currentStep));
/*if next status is same with current status, don't change anything*/
if (curStatus != nextStatus) {
#if MALI_DVFS_CLK_DEBUG
unsigned int *pRegMaliClkDiv;
unsigned int *pRegMaliMpll;
#endif
if (nextStatus > curStatus) {
#ifdef CONFIG_MALI_DVFS
update_time_in_state(curStatus);
#endif
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
/*change the clock*/
mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
} else if (nextStatus < curStatus) {
#ifdef CONFIG_MALI_DVFS
update_time_in_state(curStatus);
#endif
/*change the clock*/
mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
} else
return 0;
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE|
MALI_PROFILING_EVENT_CHANNEL_GPU|
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0);
#endif
mali_clk_put(MALI_FALSE);
#if MALI_DVFS_CLK_DEBUG
pRegMaliClkDiv = ioremap(0x1003c52c, 32);
pRegMaliMpll = ioremap(0x1003c22c, 32);
MALI_PRINT(("Mali MPLL reg:%d, CLK DIV: %d \n", *pRegMaliMpll, *pRegMaliClkDiv));
#endif
set_mali_dvfs_current_step(nextStatus);
/*for future use*/
maliDvfsStatus.pCurrentDvfs = &mali_dvfs[nextStatus];
#if CPUFREQ_LOCK_DURING_440
/* lock/unlock CPU freq by Mali */
if (mali_dvfs[nextStatus].clock >= 440)
cpufreq_lock_by_mali(400);
else
cpufreq_unlock_by_mali();
#endif
/*wait until clock and voltage is stablized*/
mali_platform_wating(MALI_DVFS_WATING); /*msec*/
}
return 0;
}
static mali_bool init_mali_clock(void)
{
mali_bool ret = MALI_TRUE;
nPowermode = MALI_POWER_MODE_DEEP_SLEEP;
if (mali_clock != 0)
return ret; /* already initialized */
mali_dvfs_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE
| _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0);
if (mali_dvfs_lock == NULL)
return _MALI_OSK_ERR_FAULT;
if (!mali_clk_get())
{
MALI_PRINT(("Error: Failed to get Mali clock\n"));
goto err_clk;
}
clk_set_parent(vpll_src_clock, ext_xtal_clock);
clk_set_parent(sclk_vpll_clock, fout_vpll_clock);
clk_set_parent(mali_parent_clock, sclk_vpll_clock);
clk_set_parent(mali_clock, mali_parent_clock);
if (!atomic_read(&clk_active)) {
if (clk_enable(mali_clock) < 0) {
MALI_PRINT(("Error: Failed to enable clock\n"));
goto err_clk;
}
atomic_set(&clk_active, 1);
}
mali_clk_set_rate((unsigned int)mali_gpu_clk, GPU_MHZ);
MALI_PRINT(("init_mali_clock mali_clock %x\n", mali_clock));
#ifdef CONFIG_REGULATOR
g3d_regulator = regulator_get(NULL, "vdd_g3d");
if (IS_ERR(g3d_regulator))
{
MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n"));
ret = MALI_FALSE;
goto err_regulator;
}
mali_gpu_vol = get_match_volt(ID_G3D, mali_gpu_clk * GPU_ASV_VOLT);
mali_runtime_resume.vol = get_match_volt(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT);
regulator_enable(g3d_regulator);
mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol);
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT));
#endif
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE|
MALI_PROFILING_EVENT_CHANNEL_GPU|
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0);
#endif
mali_clk_put(MALI_FALSE);
return MALI_TRUE;
#ifdef CONFIG_REGULATOR
err_regulator:
regulator_put(g3d_regulator);
#endif
err_clk:
mali_clk_put(MALI_TRUE);
return ret;
}
static int exynos5_devfreq_int_probe(struct platform_device *pdev)
{
int ret = 0;
struct devfreq_data_int *data;
struct devfreq_notifier_block *devfreq_nb;
struct exynos_devfreq_platdata *plat_data;
data = kzalloc(sizeof(struct devfreq_data_int), GFP_KERNEL);
if (data == NULL) {
pr_err("DEVFREQ(INT) : Failed to allocate private data\n");
ret = -ENOMEM;
goto err_data;
}
exynos5433_devfreq_int_init(data);
data->initial_freq = exynos5_devfreq_int_profile.initial_freq;
exynos5_devfreq_int_profile.freq_table = kzalloc(sizeof(int) * data->max_state, GFP_KERNEL);
if (exynos5_devfreq_int_profile.freq_table == NULL) {
pr_err("DEVFREQ(INT) : Failed to allocate freq table\n");
ret = -ENOMEM;
goto err_freqtable;
}
ret = exynos5_init_int_table(&pdev->dev, data);
if (ret)
goto err_inittable;
platform_set_drvdata(pdev, data);
mutex_init(&data->lock);
data->target_volt = get_match_volt(ID_INT, DEVFREQ_INITIAL_FREQ);
data->volt_constraint_isp = 0;
data->volt_offset = 0;
int_dev =
data->dev = &pdev->dev;
data->vdd_int = regulator_get(NULL, "vdd_int");
data->devfreq = devfreq_add_device(data->dev,
&exynos5_devfreq_int_profile,
"simple_ondemand",
&exynos5_devfreq_int_governor_data);
devfreq_nb = kzalloc(sizeof(struct devfreq_notifier_block), GFP_KERNEL);
if (devfreq_nb == NULL) {
pr_err("DEVFREQ(INT) : Failed to allocate notifier block\n");
ret = -ENOMEM;
goto err_nb;
}
devfreq_nb->df = data->devfreq;
devfreq_nb->nb.notifier_call = exynos5_devfreq_int_notifier;
exynos5433_devfreq_register(&devfreq_int_exynos);
exynos5433_ppmu_register_notifier(INT, &devfreq_nb->nb);
plat_data = data->dev->platform_data;
data->default_qos = plat_data->default_qos;
data->devfreq->min_freq = plat_data->default_qos;
data->devfreq->max_freq = devfreq_int_opp_list[0].freq;
register_reboot_notifier(&exynos5_int_reboot_notifier);
#ifdef CONFIG_EXYNOS_THERMAL
data->tmu_notifier.notifier_call = exynos5_devfreq_int_tmu_notifier;
exynos_tmu_add_notifier(&data->tmu_notifier);
#endif
data->use_dvfs = true;
return ret;
err_nb:
devfreq_remove_device(data->devfreq);
err_inittable:
kfree(exynos5_devfreq_int_profile.freq_table);
err_freqtable:
kfree(data);
err_data:
return ret;
}
