int board_eth_init(bd_t *bis) { /* Use Misc PLL for the source of ethernet */ eth_clk_set(ETH_CLKSRC_MISC_CLK, get_misc_pll_clk(), (50 * CLK_1M)); /* Use Internal clock output from GPIOY0*/ eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_OUT_GPIOY0_REG6_17, 0); /*disalbe*/ //reset:LCD_G5 writel(readl(ETH_PLL_CNTL) & ~(1 << 0), ETH_PLL_CNTL); // Disable the Ethernet clocks // --------------------------------------------- // Test 50Mhz Input Divide by 2 // --------------------------------------------- // Select divide by 2 writel(readl(ETH_PLL_CNTL) | (0 << 3), ETH_PLL_CNTL); // desc endianess "same order" writel(readl(ETH_PLL_CNTL) | (0 << 2), ETH_PLL_CNTL); // data endianess "little" writel(readl(ETH_PLL_CNTL) | (1 << 1), ETH_PLL_CNTL); // divide by 2 for 100M writel(readl(ETH_PLL_CNTL) | (1 << 0), ETH_PLL_CNTL); // enable Ethernet clocks udelay(100); /* reset phy with GPIOA_23*/ set_gpio_mode(GPIOA_bank_bit0_27(23), GPIOA_bit_bit0_27(23), GPIO_OUTPUT_MODE); set_gpio_val(GPIOA_bank_bit0_27(23), GPIOA_bit_bit0_27(23), 0); udelay(100); //GPIOE_bank_bit16_21(16) reset end; set_gpio_val(GPIOA_bank_bit0_27(23), GPIOA_bit_bit0_27(23), 1); udelay(100); //waiting reset end; aml_eth_init(bis); return 0; }
static void __init device_clk_setting(void) { /*Demod CLK for eth and sata*/ //demod_apll_setting(0,1200*CLK_1M); /*eth clk*/ #ifdef NET_EXT_CLK eth_clk_set(7, (50 * CLK_1M), (50 * CLK_1M), 1); #else eth_clk_set(ETH_CLKSRC_MISC_CLK, get_misc_pll_clk(), (50 * CLK_1M), 0); #endif //eth_clk_set(1, get_system_clk(), (50 * CLK_1M), 0); }
int board_eth_init(bd_t *bis) { unsigned v; CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_6,(3<<17));//reg6[17/18]=0 #ifdef CONFIG_NET_CLK_EXTERNAL //rmii 50 in //set clock eth_clk_set_invert(7,50*CLK_1M,50*CLK_1M); eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_IN_GPIOY0_REG6_18, 0); #else /* Use Misc PLL for the source of ethernet */ eth_clk_set(ETH_CLKSRC_MISC_CLK, get_misc_pll_clk(), (50 * CLK_1M)); /* Use Internal clock output from GPIOY0*/ eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_OUT_GPIOY0_REG6_17, 0); #endif //CONFIG_NET_CLK_EXTERNAL /*disalbe*/ //reset:LCD_G5 writel(readl(ETH_PLL_CNTL) & ~(1 << 0), ETH_PLL_CNTL); // Disable the Ethernet clocks // --------------------------------------------- // Test 50Mhz Input Divide by 2 // --------------------------------------------- // Select divide by 2 writel(readl(ETH_PLL_CNTL) | (0 << 3), ETH_PLL_CNTL); // desc endianess "same order" writel(readl(ETH_PLL_CNTL) | (0 << 2), ETH_PLL_CNTL); // data endianess "little" writel(readl(ETH_PLL_CNTL) | (1 << 1), ETH_PLL_CNTL); // divide by 2 for 100M writel(readl(ETH_PLL_CNTL) | (1 << 0), ETH_PLL_CNTL); // enable Ethernet clocks udelay(100); /* reset phy with GPIOD_7*/ set_gpio_mode(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), GPIO_OUTPUT_MODE); set_gpio_val(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), 0); udelay(2000); set_gpio_val(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), 1); udelay(2000); //waiting reset end; /* reset phy with GPIOAO_6*/ /* v = ~((1<<6)|(1<22)); writel(v,0xC81000024); udelay(2000); v |= (1<22); writel(v,0xC81000024); udelay(2000); //waiting reset end; */ aml_eth_init(bis); return 0; }