static void mpu_init_34xx(u32 sil_index, u32 clk_index) { struct prcm *prcm_base = (struct prcm *)PRCM_BASE; dpll_param *ptr = (dpll_param *) get_mpu_dpll_param(); /* Moving to the right sysclk and ES rev base */ ptr = ptr + (3 * clk_index) + sil_index; /* MPU DPLL (unlocked already) */ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2); /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8); /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n); /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */ clrsetbits_le32(&prcm_base->clken_pll_mpu, 0x000000F0, ptr->fsel << 4); }
static void mpu_dpll_init_34XX(int clk_index, int sil_index) { dpll_param *dpll_param_p; /* Getting the base address to MPU DPLL param table*/ dpll_param_p = (dpll_param *)get_mpu_dpll_param(); /* Moving it to the right sysclk and ES rev base */ dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; /* MPU DPLL (unlocked already) */ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); }
static dpll_param *_get_mpu_dpll(int clk_index, int sil_index) { dpll_param *ret = (dpll_param *)get_mpu_dpll_param(); ret += (MAX_SIL_INDEX * clk_index) + sil_index; return ret; }