static __init unsigned long get_m48t35_time(void)
{
unsigned int year, month, date, hour, min, sec;
struct m48t35_rtc *rtc;
nasid_t nid;
nid = get_nasid();
rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base +
IOC3_BYTEBUS_DEV0);
rtc->control |= M48T35_RTC_READ;
sec = rtc->sec;
min = rtc->min;
hour = rtc->hour;
date = rtc->date;
month = rtc->month;
year = rtc->year;
rtc->control &= ~M48T35_RTC_READ;
BCD_TO_BIN(sec);
BCD_TO_BIN(min);
BCD_TO_BIN(hour);
BCD_TO_BIN(date);
BCD_TO_BIN(month);
BCD_TO_BIN(year);
year += 1970;
return mktime(year, month, date, hour, min, sec);
}
static inline struct ioc3_uartregs *console_uart(void)
{
struct ioc3 *ioc3;
nasid_t nasid;
nasid = (master_nasid == INVALID_NASID) ? get_nasid() : master_nasid;
ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(nasid)->memory_base;
return &ioc3->sregs.uarta;
}
static inline void ioc3_eth_init(void)
{
struct ioc3 *ioc3;
nasid_t nid;
nid = get_nasid();
ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base;
ioc3->eier = 0;
}
static int __init ip27_setup(void)
{
hubreg_t p, e, n_mode;
nasid_t nid;
ip27_setup_console();
ip27_reboot_setup();
/*
* hub_rtc init and cpu clock intr enabled for later calibrate_delay.
*/
nid = get_nasid();
printk("IP27: Running on node %d.\n", nid);
p = LOCAL_HUB_L(PI_CPU_PRESENT_A) & 1;
e = LOCAL_HUB_L(PI_CPU_ENABLE_A) & 1;
printk("Node %d has %s primary CPU%s.\n", nid,
p ? "a" : "no",
e ? ", CPU is running" : "");
p = LOCAL_HUB_L(PI_CPU_PRESENT_B) & 1;
e = LOCAL_HUB_L(PI_CPU_ENABLE_B) & 1;
printk("Node %d has %s secondary CPU%s.\n", nid,
p ? "a" : "no",
e ? ", CPU is running" : "");
/*
* Try to catch kernel missconfigurations and give user an
* indication what option to select.
*/
n_mode = LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_MORENODES_MASK;
printk("Machine is in %c mode.\n", n_mode ? 'N' : 'M');
#ifdef CONFIG_SGI_SN0_N_MODE
if (!n_mode)
panic("Kernel compiled for M mode.");
#else
if (n_mode)
panic("Kernel compiled for N mode.");
#endif
ioc3_sio_init();
ioc3_eth_init();
per_cpu_init();
set_io_port_base(IO_BASE);
board_time_init = ip27_time_init;
return 0;
}
static void sn_ack_irq(unsigned int irq)
{
uint64_t event_occurred, mask = 0;
int nasid;
irq = irq & 0xff;
nasid = get_nasid();
event_occurred =
HUB_L((uint64_t *) GLOBAL_MMR_ADDR(nasid, SH_EVENT_OCCURRED));
mask = event_occurred & SH_ALL_INT_MASK;
HUB_S((uint64_t *) GLOBAL_MMR_ADDR(nasid, SH_EVENT_OCCURRED_ALIAS),
mask);
__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
move_irq(irq);
}
module_t *module_add_node(moduleid_t id, cnodeid_t n)
{
module_t *m;
int i;
DPRINTF("module_add_node: id=%x node=%d\n", id, n);
if ((m = module_lookup(id)) == 0) {
#ifndef CONFIG_IA64_SGI_IO
m = kmem_zalloc_node(sizeof (module_t), KM_NOSLEEP, n);
#else
m = kmalloc(sizeof (module_t), GFP_KERNEL);
memset(m, 0 , sizeof(module_t));
printk("Module nodecnt = %d\n", m->nodecnt);
#endif
ASSERT_ALWAYS(m);
DPRINTF("module_add_node: m=0x%p\n", m);
m->id = id;
spin_lock_init(&m->lock);
init_MUTEX_LOCKED(&m->thdcnt);
printk("Set elsc to 0x%p on node %d\n", &m->elsc, get_nasid());
set_elsc(&m->elsc);
elsc_init(&m->elsc, COMPACT_TO_NASID_NODEID(n));
spin_lock_init(&m->elsclock);
/* Insert in sorted order by module number */
for (i = nummodules; i > 0 && modules[i - 1]->id > id; i--)
modules[i] = modules[i - 1];
modules[i] = m;
nummodules++;
}
m->nodes[m->nodecnt++] = n;
printk("module_add_node: module %x now has %d nodes\n", id, m->nodecnt);
DPRINTF("module_add_node: module %x now has %d nodes\n", id, m->nodecnt);
return m;
}
void __init plat_mem_setup(void)
{
hubreg_t p, e, n_mode;
nasid_t nid;
ip27_reboot_setup();
/*
*/
nid = get_nasid();
printk("IP27: Running on node %d.\n", nid);
p = LOCAL_HUB_L(PI_CPU_PRESENT_A) & 1;
e = LOCAL_HUB_L(PI_CPU_ENABLE_A) & 1;
printk("Node %d has %s primary CPU%s.\n", nid,
p ? "a" : "no",
e ? ", CPU is running" : "");
p = LOCAL_HUB_L(PI_CPU_PRESENT_B) & 1;
e = LOCAL_HUB_L(PI_CPU_ENABLE_B) & 1;
printk("Node %d has %s secondary CPU%s.\n", nid,
p ? "a" : "no",
e ? ", CPU is running" : "");
/*
*/
n_mode = LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_MORENODES_MASK;
printk("Machine is in %c mode.\n", n_mode ? 'N' : 'M');
#ifdef CONFIG_SGI_SN_N_MODE
if (!n_mode)
panic("Kernel compiled for M mode.");
#else
if (n_mode)
panic("Kernel compiled for N mode.");
#endif
ioc3_eth_init();
per_cpu_init();
set_io_port_base(IO_BASE);
}
static int set_rtc_mmss(unsigned long nowtime)
{
int retval = 0;
int real_seconds, real_minutes, cmos_minutes;
struct m48t35_rtc *rtc;
nasid_t nid;
nid = get_nasid();
rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base +
IOC3_BYTEBUS_DEV0);
rtc->control |= M48T35_RTC_READ;
cmos_minutes = rtc->min;
BCD_TO_BIN(cmos_minutes);
rtc->control &= ~M48T35_RTC_READ;
/*
* Since we're only adjusting minutes and seconds, don't interfere with
* hour overflow. This avoids messing with unknown time zones but
* requires your RTC not to be off by more than 15 minutes
*/
real_seconds = nowtime % 60;
real_minutes = nowtime / 60;
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
real_minutes += 30; /* correct for half hour time zone */
real_minutes %= 60;
if (abs(real_minutes - cmos_minutes) < 30) {
BIN_TO_BCD(real_seconds);
BIN_TO_BCD(real_minutes);
rtc->control |= M48T35_RTC_SET;
rtc->sec = real_seconds;
rtc->min = real_minutes;
rtc->control &= ~M48T35_RTC_SET;
} else {
printk(KERN_WARNING
"set_rtc_mmss: can't update from %d to %d\n",
cmos_minutes, real_minutes);
retval = -1;
}
return retval;
}
/* Extracted from the IOC3 meta driver. FIXME. */
static inline void ioc3_sio_init(void)
{
struct ioc3 *ioc3;
nasid_t nid;
long loops;
nid = get_nasid();
ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base;
ioc3->sscr_a = 0; /* PIO mode for uarta. */
ioc3->sscr_b = 0; /* PIO mode for uartb. */
ioc3->sio_iec = ~0;
ioc3->sio_ies = (SIO_IR_SA_INT | SIO_IR_SB_INT);
loops=1000000; while(loops--);
ioc3->sregs.uarta.iu_fcr = 0;
ioc3->sregs.uartb.iu_fcr = 0;
loops=1000000; while(loops--);
}
void __init cpu_time_init(void)
{
lboard_t *board;
klcpu_t *cpu;
int cpuid;
/* Don't use ARCS. ARCS is fragile. Klconfig is simple and sane. */
board = find_lboard(KL_CONFIG_INFO(get_nasid()), KLTYPE_IP27);
if (!board)
panic("Can't find board info for myself.");
cpuid = LOCAL_HUB_L(PI_CPU_NUM) ? IP27_CPU0_INDEX : IP27_CPU1_INDEX;
cpu = (klcpu_t *) KLCF_COMP(board, cpuid);
if (!cpu)
panic("No information about myself?");
printk("CPU %d clock is %dMHz.\n", smp_processor_id(), cpu->cpu_speed);
set_c0_status(SRB_TIMOCLK);
}
static int __init rtc_init(void)
{
unsigned long flags;
nasid_t nid;
nid = get_nasid();
rtc = (struct m48t35_rtc *)
KL_CONFIG_CH_CONS_INFO(nid)->memory_base + IOC3_BYTEBUS_DEV0;
printk(KERN_INFO "Real Time Clock Driver v%s\n", RTC_VERSION);
if (misc_register(&rtc_dev))
return -ENODEV;
create_proc_read_entry ("rtc", 0, NULL, rtc_read_proc, NULL);
save_flags(flags);
cli();
restore_flags(flags);
rtc_freq = 1024;
return 0;
}
void __init ip27_setup(void)
{
nasid_t nid;
hubreg_t p, e;
ip27_setup_console();
ip27_reboot_setup();
num_bridges = 0;
/*
* hub_rtc init and cpu clock intr enabled for later calibrate_delay.
*/
DBG("ip27_setup(): Entered.\n");
nid = get_nasid();
printk("IP27: Running on node %d.\n", nid);
p = LOCAL_HUB_L(PI_CPU_PRESENT_A) & 1;
e = LOCAL_HUB_L(PI_CPU_ENABLE_A) & 1;
printk("Node %d has %s primary CPU%s.\n", nid,
p ? "a" : "no",
e ? ", CPU is running" : "");
p = LOCAL_HUB_L(PI_CPU_PRESENT_B) & 1;
e = LOCAL_HUB_L(PI_CPU_ENABLE_B) & 1;
printk("Node %d has %s secondary CPU%s.\n", nid,
p ? "a" : "no",
e ? ", CPU is running" : "");
verify_mode();
ioc3_sio_init();
ioc3_eth_init();
per_cpu_init();
set_io_port_base(IO_BASE);
board_be_init = ip27_be_init;
board_time_init = ip27_time_init;
}
static int __init rtc_init(void)
{
nasid_t nid;
nid = get_nasid();
rtc = (struct m48t35_rtc *)
(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + IOC3_BYTEBUS_DEV0);
printk(KERN_INFO "Real Time Clock Driver v%s\n", RTC_VERSION);
if (misc_register(&rtc_dev)) {
printk(KERN_ERR "rtc: cannot register misc device.\n");
return -ENODEV;
}
if (!create_proc_read_entry("driver/rtc", 0, NULL, rtc_read_proc, NULL)) {
printk(KERN_ERR "rtc: cannot create /proc/rtc.\n");
misc_deregister(&rtc_dev);
return -ENOENT;
}
rtc_freq = 1024;
return 0;
}
/*
* For the given device, initialize the addresses for both the Device(x) Flush
* Write Buffer register and the Xbow Flush Register for the port the PCI bus
* is connected.
*/
static void
set_flush_addresses(struct pci_dev *device_dev,
struct sn_device_sysdata *device_sysdata)
{
pciio_info_t pciio_info = pciio_info_get(device_sysdata->vhdl);
pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info);
pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
bridge_t *bridge = pcibr_soft->bs_base;
device_sysdata->dma_buf_sync = (volatile unsigned int *)
&(bridge->b_wr_req_buf[pciio_slot].reg);
device_sysdata->xbow_buf_sync = (volatile unsigned int *)
XBOW_PRIO_LINKREGS_PTR(NODE_SWIN_BASE(get_nasid(), 0),
pcibr_soft->bs_xid);
#ifdef DEBUG
printk("set_flush_addresses: dma_buf_sync %p xbow_buf_sync %p\n",
device_sysdata->dma_buf_sync, device_sysdata->xbow_buf_sync);
while((volatile unsigned int )*device_sysdata->dma_buf_sync);
while((volatile unsigned int )*device_sysdata->xbow_buf_sync);
#endif
}
static void sn_end_irq(unsigned int irq)
{
int nasid;
int ivec;
uint64_t event_occurred;
ivec = irq & 0xff;
if (ivec == SGI_UART_VECTOR) {
nasid = get_nasid();
event_occurred = HUB_L((uint64_t *) GLOBAL_MMR_ADDR
(nasid, SH_EVENT_OCCURRED));
/* If the UART bit is set here, we may have received an
* interrupt from the UART that the driver missed. To
* make sure, we IPI ourselves to force us to look again.
*/
if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
IA64_IPI_DM_INT, 0);
}
}
__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
if (sn_force_interrupt_flag)
force_interrupt(irq);
}
/*
* Map the physical node id to a virtual node id (virtual node ids are contiguous).
*/
cnodeid_t get_compact_nodeid(void)
{
return NASID_TO_COMPACT_NODEID(get_nasid());
}
void
set_elsc(elsc_t *p)
{
Elsc[get_nasid()] = p;
}
