static void update_operand_contents(OperandVal *opnd) {
if (opnd->type == TRegister) {
int regnum = get_regnum(*opnd);
switch (opnd->addr) {
case ax_reg:
case bx_reg:
case cx_reg:
case dx_reg:
case bp_reg:
case sp_reg:
case si_reg:
case di_reg:
opnd->value = cpu_single_env->regs[regnum] & 0xFFFF;
break;
case al_reg:
case bl_reg:
case cl_reg:
case dl_reg:
opnd->value = cpu_single_env->regs[regnum] & 0xFF;
break;
case ah_reg:
case bh_reg:
case ch_reg:
case dh_reg:
opnd->value = (cpu_single_env->regs[regnum] & 0xFF00) >> 8;
break;
default:
opnd->value = cpu_single_env->regs[regnum];
break;
}
} else if (opnd->type == TMemLoc) {
static RObject *rstack_getrobj (RStack *rs, GCObject *o) {
int regnum = get_regnum(o);
Region *r = &rs->regions[regnum];
RObject *top = r->top, *base = r->base;
lua_assert(regnum > 0 && regnum < RStack_REGIONS);
while (top != base) {
--top;
if (top->body == o)
return top;
}
return NULL;
}
void put_rom(char assm[], ltable table, instr &inst, uint romindex){
char *asmtok[10];
char delims[] = " \t\r\n";
while(*assm == ' ' || *assm == '\t')
assm++;
asmtok[0] = strtok(assm, delims);
for(int itr=1; (asmtok[itr] = strtok(NULL, delims)) != NULL;itr++);
enum {r,i,j, branch, none} format;
#define op(str,code,form) \
else if (strcmp(asmtok[0],#str) == 0){opcode = code;format = form;}
uint8_t opcode;
// 擬似命令setl
if(strcmp(assm,"setl") == 0){
int16_t reg = get_regnum(asmtok[1]), addr = table.get_index(asmtok[2]);
inst.set(ADDI, reg, 0, addr);
return;
}
op(add , ADD, r)
op(sub , SUB, r)
op(addf, ADDF, r)
op(subf, SUBF, r)
op(mulf, MULF, r)
op(divf, DIVF, r)
op(sqrt, SQRT, r)
op(addi, ADDI, i)
op(subi, SUBI, i)
op(and , AND, r)
op(or , OR , r)
op(nor , NOR , r)
op(xor , XOR , r)
op(andi, ANDI, i)
op(ori , ORI , i)
op(sll , SLL , r)
op(srl , SRL , r)
op(sra , SRA , r)
op(cmp , CMP , r)
op(cmpf, CMPF, r)
op(mvr , MVR , r)
op(mvf , MVF , r)
op(mvrf, MVRF, r)
op(mvfr, MVFR, r)
op(lui , LUI , i)
op(lli , LLI , i)
op(luif, LUIF, i)
op(llif, LLIF, i)
op(lw , LW , r)
op(lwi , LWI , r)
op(sw , SW , r)
op(swi , SWI , i)
op(lwf , LWF , r)
op(lwif, LWIF, i)
op(swf , SWF , r)
op(swif, SWIF, i)
op(j , J , j)
op(jl , JL , j)
op(jr , JR , r)
op(jlr , JLR , r)
op(beq , BEQ , branch)
op(bne , BNE , branch)
op(beqf, BEQF, branch)
op(bnef, BNEF, branch)
op(nop , NOP , none)
op(dbg , DBG , none)
op(rst , RST , none)
op(halt, HALT, none)
op(in , IN , r)
op(inf, INF , r)
op(outa,OUTA, r)
op(outb,OUTB, r)
op(outc,OUTC, r)
op(outd,OUTD, r)
op(outaf,OUTAF, r)
op(outbf,OUTBF, r)
op(outcf,OUTCF, r)
op(outdf,OUTDF, r)
else {
cerr << "unknown opcode: " << asmtok[0] << '\n';
exit(1);
}
;
#undef op
if(format == none){
inst.set(opcode);
}
else if(format == j){
int16_t imm;
imm = table.get_index(asmtok[1]);
inst.set_imm(opcode, imm);
}
else if(format == branch){
uint8_t args[2] = {0, 0};
for(int itr=0; itr < 2;itr++){
args[itr] = (uint8_t)get_regnum(asmtok[itr+1]);
}
int16_t imm;
imm = table.get_index(asmtok[3]) - romindex - 1;
if(romindex == 0)imm--;
inst.set(opcode, args[0], args[1], imm);
}
else {
int args[3] = {0, 0, 0};
for(int itr=0; asmtok[itr+1] != NULL;itr++){
args[itr] = get_regnum(asmtok[itr+1]);
}
inst.set(opcode, (uint8_t)args[0], (uint8_t)args[1], (int16_t)args[2]);
}
}
