static int cfg_md_mem_layout(int md_id) { unsigned int md_len; unsigned int dsp_len; unsigned int smem_base_before_map; unsigned int md_rom_mem_base; int ret = 0; #ifdef MD_IMG_SIZE_ADJUST_BY_VER if(get_modem_support(md_id) == modem_2g) md_len = DSP_REGION_BASE_2G; else md_len = DSP_REGION_BASE_3G; dsp_len = DSP_REGION_LEN; #else //md_len = MD_IMG_RESRVED_SIZE + MD_RW_MEM_RESERVED_SIZE; md_len = get_resv_mem_size_for_md(md_id); dsp_len = 0; #endif // MD image md_mem_layout_tab[md_id].md_region_phy = get_md_mem_start_addr(md_id); md_mem_layout_tab[md_id].md_region_size = md_len; md_rom_mem_base = md_mem_layout_tab[md_id].md_region_phy; // DSP image md_mem_layout_tab[md_id].dsp_region_phy = get_md_mem_start_addr(md_id) + md_len; md_mem_layout_tab[md_id].dsp_region_size = dsp_len; // Share memory smem_base_before_map = get_md_share_mem_start_addr(md_id); // Store address before mapping md_mem_layout_tab[md_id].smem_region_phy_before_map = smem_base_before_map; md_mem_layout_tab[md_id].smem_region_size = get_resv_share_mem_size_for_md(md_id); #ifdef ENABLE_SW_MEM_REMAP md_2_ap_phy_addr_offset_fixed = (smem_base_before_map&0xFE000000)-0x40000000;// 32M align address - 0x40000000 md_mem_layout_tab[md_id].smem_region_phy = smem_base_before_map; #else md_mem_layout_tab[md_id].smem_region_phy = smem_base_before_map - get_smem_base_addr(md_id) + 0x40000000; // 0x40000000 is BANK4 start addr //set ap share memory remap set_ap_smem_remap(md_id, 0x40000000, smem_base_before_map); #endif // Set md share memory remapping set_md_smem_remap(md_id, 0x40000000, smem_base_before_map); // Set md image and rw runtime memory remapping set_md_rom_rw_mem_remap(md_id, 0x00000000, md_rom_mem_base); return ret; }
static int cfg_md_mem_layout(int md_id) { unsigned int md_len; unsigned int dsp_len; unsigned int smem_base_before_map; unsigned int md_rom_mem_base; int ret = 0; #ifdef MD_IMG_SIZE_ADJUST_BY_VER if(get_ap_img_ver() == AP_IMG_2G) md_len = DSP_REGION_BASE_2G; else if(get_ap_img_ver() == AP_IMG_3G) md_len = DSP_REGION_BASE_3G; else md_len = DSP_REGION_BASE_3G; dsp_len = DSP_REGION_LEN; #else md_len = MD_IMG_RESRVED_SIZE + MD_RW_MEM_RESERVED_SIZE; dsp_len = 0; #endif // MD image md_mem_layout_tab[md_id].md_region_phy = get_md_mem_start_addr(md_id); md_mem_layout_tab[md_id].md_region_size = md_len; md_rom_mem_base = md_mem_layout_tab[md_id].md_region_phy; // DSP image md_mem_layout_tab[md_id].dsp_region_phy = get_md_mem_start_addr(md_id) + md_len; md_mem_layout_tab[md_id].dsp_region_size = dsp_len; // Share memory smem_base_before_map = get_md_share_mem_start_addr(md_id); md_mem_layout_tab[md_id].smem_region_phy = smem_base_before_map - get_smem_base_addr(md_id) + 0x40000000; // 0x40000000 is BANK4 start addr md_mem_layout_tab[md_id].smem_region_size = CCCI_SHARED_MEM_SIZE; // Store address before mapping md_mem_layout_tab[md_id].smem_region_phy_before_map = smem_base_before_map; // Set share memory remapping set_ap_smem_remap(md_id, 0x40000000, smem_base_before_map); set_md_smem_remap(md_id, 0x40000000, smem_base_before_map); // Set md image and rw runtime memory remapping set_md_rom_rw_mem_remap(md_id, 0x00000000, md_rom_mem_base); return ret; }