/*
* Initialize Local Bus
*/
void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
gur->lbiuiplldcr1 = 0x00078080;
if (clkdiv == 16) {
gur->lbiuiplldcr0 = 0x7c0f1bf0;
} else if (clkdiv == 8) {
gur->lbiuiplldcr0 = 0x6c0f1bf0;
} else if (clkdiv == 4) {
gur->lbiuiplldcr0 = 0x5c0f1bf0;
}
lbc->lcrr |= 0x00030000;
asm("sync;isync;msync");
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
}
int get_clocks (void)
{
sys_info_t sys_info;
#if defined(CONFIG_CPM2)
volatile immap_t *immap = (immap_t *) CFG_IMMR;
uint sccr, dfbrg;
/* set VCO = 4 * BRG */
immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc;
sccr = immap->im_cpm.im_cpm_intctl.sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
#if defined(CONFIG_CPM2)
gd->vco_out = 2*sys_info.freqSystemBus;
gd->cpm_clk = gd->vco_out / 2;
gd->scc_clk = gd->vco_out / 4;
gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
#endif
if(gd->cpu_clk != 0) return (0);
else return (1);
}
int checkboard (void)
{
sys_info_t sysinfo;
char buf[32];
get_sys_info (&sysinfo);
#ifdef CONFIG_SBC8560
printf ("Board: Wind River SBC8560 Board\n");
#else
printf ("Board: Wind River SBC8540 Board\n");
#endif
printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
printf ("\tLBC: %s MHz\n",
strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
} else {
printf("\tLBC: unknown\n");
}
printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
return (0);
}
int get_clocks(void)
{
sys_info_t sys_info;
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
gd->arch.lbc_clk = sys_info.freqLocalBus;
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
* there is no pattern that can be used to determine the frequency, so
* the only choice is to look up the actual SOC number and use the value
* for that SOC. This information is taken from application note
* AN2919.
*/
#ifdef CONFIG_MPC8610
gd->arch.i2c1_clk = sys_info.freqSystemBus;
#else
gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
#endif
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
if (gd->cpu_clk != 0)
return 0;
else
return 1;
}
/*
* Initialize Local Bus
*/
void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & 0x0f) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
if (clkdiv == 16) {
gur->lbiuiplldcr0 = 0x7c0f1bf0;
} else if (clkdiv == 8) {
gur->lbiuiplldcr0 = 0x6c0f1bf0;
} else if (clkdiv == 4) {
gur->lbiuiplldcr0 = 0x5c0f1bf0;
}
lbc->lcrr |= 0x00030000;
asm("sync;isync;msync");
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
}
/*
* Initialize Local Bus
*/
void local_bus_init (void)
{
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
sys_info_t sysinfo;
uint clkdiv;
uint lbc_mhz;
uint lcrr = CONFIG_SYS_LBC_LCRR;
get_sys_info (&sysinfo);
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
if (lbc_mhz >= 66)
lcrr &= ~LCRR_DBYP; /* DLL Enabled */
else
lcrr |= LCRR_DBYP; /* DLL Bypass */
out_be32 (&lbc->lcrr, lcrr);
asm ("sync;isync;msync");
out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
/* Init UPMA for FPGA access */
out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
/* Init UPMB for Lime controller access */
out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
char *s = getenv("serial#");
#ifdef DISPLAY_BOARD_INFO
sys_info_t sysinfo;
#endif
puts("Board: Quad100hd");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
#ifdef DISPLAY_BOARD_INFO
/* taken from ppcboot */
get_sys_info(&sysinfo);
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv *
1000000));
printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
#endif
return 0;
}
static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
{
PPC4xx_SYS_INFO sys_info;
u8 val;
get_sys_info(&sys_info);
/* Correct UART frequency in bd-info struct now that
* the UART divisor is available
*/
#ifdef CFG_EXT_SERIAL_CLOCK
gd->uart_clk = CFG_EXT_SERIAL_CLOCK;
#else
gd->uart_clk = sys_info.freqUART / udiv;
#endif
out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */
out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */
out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */
out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */
val = in_8((u8 *)base + UART_LSR); /* clear line status */
val = in_8((u8 *)base + UART_RBR); /* read receive buffer */
out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */
out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */
}
void board_add_ram_info(int use_default)
{
PPC4xx_SYS_INFO board_cfg;
u32 val;
mfsdram(DDR0_22, val);
val &= DDR0_22_CTRL_RAW_MASK;
switch (val) {
case DDR0_22_CTRL_RAW_ECC_DISABLE:
puts(" (ECC disabled");
break;
case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
puts(" (ECC check only");
break;
case DDR0_22_CTRL_RAW_NO_ECC_RAM:
puts(" (no ECC ram");
break;
case DDR0_22_CTRL_RAW_ECC_ENABLE:
puts(" (ECC enabled");
break;
}
get_sys_info(&board_cfg);
printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
mfsdram(DDR0_03, val);
val = DDR0_03_CASLAT_DECODE(val);
printf(", CL%d)", val);
}
/*
* Initialize Local Bus
*/
void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
if (clkdiv == 16) {
gur->lbiuiplldcr0 = 0x7c0f1bf0;
} else if (clkdiv == 8) {
gur->lbiuiplldcr0 = 0x6c0f1bf0;
} else if (clkdiv == 4) {
gur->lbiuiplldcr0 = 0x5c0f1bf0;
}
lbc->lcrr |= 0x00030000;
asm("sync;isync;msync");
}
/*
* Get timebase clock frequency
*/
unsigned long
get_tbclk(void)
{
sys_info_t sys_info;
get_sys_info(&sys_info);
return (sys_info.freqSystemBus + 3L) / 4L;
}
int main()
{
float f[10]={0.0};
int i;
int j;
get_sys_info(f,10);
usleep(600000);
for(j=0;j<10;++j){
get_sys_info(f,10);
for(i=0;i<10;++i)
printf("%.1f\t",f[i]);
printf("\n--------------\n");
sleep(1);
}
return 0;
}
void ft_cpu_setup(void *blob, bd_t *bd)
{
sys_info_t sys_info;
int off, ndepth = 0;
get_sys_info(&sys_info);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency",
bd->bi_intfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency",
bd->bi_intfreq, 1);
do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
sys_info.freqEBC, 1);
else
do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
sys_info.freqEBC, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
/*
* Fixup all UART clocks for CPU internal UARTs
* (only these UARTs are definitely clocked by gd->arch.uart_clk)
*
* These UARTs are direct childs of /plb/opb. This code
* does not touch any UARTs that are connected to the ebc.
*/
off = fdt_path_offset(blob, "/plb/opb");
while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
/*
* process all sub nodes and stop when we are back
* at the starting depth
*/
if (ndepth <= 0)
break;
/* only update direct childs */
if ((ndepth == 1) &&
(fdt_node_check_compatible(blob, off, "ns16550") == 0))
fdt_setprop(blob, off,
"clock-frequency",
(void *)&gd->arch.uart_clk, 4);
}
/*
* Fixup all ethernet nodes
* Note: aliases in the dts are required for this
*/
fdt_fixup_ethernet(blob);
/*
* Fixup all available PCIe nodes by setting the device_type property
*/
fdt_pcie_setup(blob);
}
int get_clocks (void)
{
sys_info_t sys_info;
#ifdef CONFIG_MPC8544
volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
uint sccr, dfbrg;
/* set VCO = 4 * BRG */
cpm->im_cpm_intctl.sccr &= 0xfffffffc;
sccr = cpm->im_cpm_intctl.sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
gd->mem_clk = sys_info.freqDDRBus;
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
* there is no pattern that can be used to determine the frequency, so
* the only choice is to look up the actual SOC number and use the value
* for that SOC. This information is taken from application note
* AN2919.
*/
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
gd->i2c1_clk = sys_info.freqSystemBus;
#elif defined(CONFIG_MPC8544)
/*
* On the 8544, the I2C clock is the same as the SEC clock. This can be
* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
*/
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
gd->i2c1_clk = sys_info.freqSystemBus / 3;
else
gd->i2c1_clk = sys_info.freqSystemBus / 2;
#else
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
gd->i2c1_clk = sys_info.freqSystemBus / 2;
#endif
gd->i2c2_clk = gd->i2c1_clk;
#if defined(CONFIG_CPM2)
gd->vco_out = 2*sys_info.freqSystemBus;
gd->cpm_clk = gd->vco_out / 2;
gd->scc_clk = gd->vco_out / 4;
gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
#endif
if(gd->cpu_clk != 0) return (0);
else return (1);
}
/********************************************
* get_PCI_freq
* return PCI bus freq in Hz
*********************************************/
ulong get_PCI_freq (void)
{
ulong val;
PPC405_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllPciDiv;
return val;
}
int main(int argc, char **argv)
{
get_sys_info(f[0],10);
usleep(600000);
size_mac=sizeof(struct ether_header);
size_ip=sizeof(struct ip);
///////////////////////////////////
signal(SIGINT, sigproc);
signal(SIGTERM, sigproc);
signal(SIGINT, sigproc);
//perror("what's wrong\n");
//init_loop(&shmp,&shmid,shmpath);
//init_loop(&shmp,&shmid,shmpath1);
int i;
char buf[256];
initBCBuff();
printf("1111111111111111\n");
for(i=0;i<snortnum;++i)//create shm
{
losep[i]=0LL;
sprintf(buf,"%s",shmpath);
//puts(buf);
init_loop(&shmp[i],&shmid[i],buf,i);
}
hb=init_HB(HB_MAX);
init_free_link(FREE_NODE);
init_BC();//the cache for the pro classificationd
printf("EIinit bc\n");
init_patterns();
int sockfd;
struct pcap_pkthdr pkthdr;
if ((sockfd = socket (PF_PACKET, SOCK_RAW, htons (ETH_P_ALL))) < 0)
{
printf ("create socket failed\n");
return -1;
}
if (0 != set_promisc ("eth0", sockfd))
{
printf ("Failed to set interface promisc mode\n");
}
unsigned char buffer[65535] = {0};
while (1)
{
//memset (&packet, 0x0, sizeof (packet));
memset (buffer, 0x0, sizeof (buffer));
pkthdr.caplen = recvfrom (sockfd, buffer, sizeof (buffer), 0, NULL, NULL);
my_callback(NULL,&pkthdr,buffer);
}
return 0;
}
void my_sigalarm(int sig) {
//if(do_shutdown)
// return;
get_sys_info(f[alarmnum],10);
alarmnum++;
//printf("vvvvvvvvvvv\n");
//print_stats();
alarm(ALARM_SLEEP);
signal(SIGALRM, my_sigalarm);
}
ulong get_bus_freq(ulong dummy)
{
ulong val;
sys_info_t sys_info;
get_sys_info(&sys_info);
val = sys_info.freqSystemBus;
return val;
}
void
local_bus_init(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
/*
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66Mhz, DLL bypass mode must be used.
* If localbus freq is > 133Mhz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
} else if (lbc_hz >= 133) {
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
} else {
/*
* On REV1 boards, need to change CLKDIV before enable DLL.
* Default CLKDIV is 8, change it to 4 temporarily.
*/
uint pvr = get_pvr();
uint temp_lbcdll = 0;
if (pvr == PVR_85xx_REV1) {
/* FIXME: Justify the high bit here. */
lbc->lcrr = 0x10000004;
}
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
udelay(200);
/*
* Sample LBC DLL ctrl reg, upshift it to set the
* override bits.
*/
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm("sync;isync;msync");
}
}
/********************************************
* get_OPB_freq
* return OPB bus freq in Hz
*********************************************/
ulong get_OPB_freq (void)
{
ulong val = 0;
PPC405_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllOpbDiv;
return val;
}
/*
* Get timebase clock frequency
*/
unsigned long get_tbclk (void)
{
#if !defined(CONFIG_IOP480)
sys_info_t sys_info;
get_sys_info(&sys_info);
return (sys_info.freqProcessor);
#else
return (66000000);
#endif
}
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
{
sys_info_t sysinfo;
char buf[32];
size_t ddr_size;
fsl_ddr_cfg_regs_t ddr_cfg_regs = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
#endif
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
get_sys_info(&sysinfo);
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freq_ddrbus));
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
};
return ddr_size;
}
static void serial_divs (int baudrate, unsigned long *pudiv,
unsigned short *pbdiv)
{
sys_info_t sysinfo;
unsigned long div; /* total divisor udiv * bdiv */
unsigned long umin; /* minimum udiv */
unsigned short diff; /* smallest diff */
unsigned long udiv; /* best udiv */
unsigned short idiff; /* current diff */
unsigned short ibdiv; /* current bdiv */
unsigned long i;
unsigned long est; /* current estimate */
unsigned long plloutb;
unsigned long cpr_pllc;
u32 reg;
/* check the pll feedback source */
mfcpr(cprpllc, cpr_pllc);
get_sys_info(&sysinfo);
plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
udiv = 256; /* Assume lowest possible serial clk */
div = plloutb / (16 * baudrate); /* total divisor */
umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
diff = 256; /* highest possible */
/* i is the test udiv value -- start with the largest
* possible (256) to minimize serial clock and constrain
* search to umin.
*/
for (i = 256; i > umin; i--) {
ibdiv = div / i;
est = i * ibdiv;
idiff = (est > div) ? (est-div) : (div-est);
if (idiff == 0) {
udiv = i;
break; /* can't do better */
} else if (idiff < diff) {
udiv = i; /* best so far */
diff = idiff; /* update lowest diff*/
}
}
*pudiv = udiv;
mfcpr(cprperd0, reg);
reg &= ~0x0000ffff;
reg |= ((udiv - 0) << 8) | (udiv - 0);
mtcpr(cprperd0, reg);
*pbdiv = div / udiv;
}
int get_clocks (void)
{
sys_info_t sys_info;
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
gd->arch.lbc_clk = sys_info.freq_ddrbus;
return 0;
}
int get_clocks(void)
{
sys_info_t sys_info;
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
if (gd->cpu_clk != 0)
return 0;
else
return 1;
}
phys_size_t fixed_sdram (void)
{
sys_info_t sysinfo;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
get_sys_info(&sysinfo);
printf("Configuring DDR for %s MT/s data rate\n",strmhz(buf, sysinfo.freqDDRBus));
/* //kosta comment
if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
panic("Unsupported DDR data rate %s MT/s data rate\n",strmhz(buf, sysinfo.freqDDRBus));
*/ //end kosta comment
//kosta_add
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_mpcboard , sizeof(ddr_cfg_regs));
cpu = gd->cpu;
// P1020 and it's derivatives support max 32bit DDR width
/* //kosta_comment
if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
ddr_cfg_regs.cs[0].bnds = 0x0000001F;
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
}
else
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
*/ //end Kosta comment
//MPC_BOARD 32 bit memory device
ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
ddr_cfg_regs.cs[0].bnds = 0x0000001F;
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
return ddr_size;
}
int checkboard (void)
{
sys_info_t sysinfo;
get_sys_info (&sysinfo);
printf ("Board: IBM 440GX Evaluation Board\n");
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
int checkboard(void)
{
sys_info_t sysinfo;
get_sys_info(&sysinfo);
printf("Board: AMCC YELLOWSTONE\n");
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
return (0);
}
void board_add_ram_info(int use_default)
{
PPC4xx_SYS_INFO board_cfg;
u32 val;
if (is_ecc_enabled())
puts(" (ECC");
else
puts(" (ECC not");
get_sys_info(&board_cfg);
printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
mfsdram(DDR0_03, val);
val = DDR0_03_CASLAT_DECODE(val);
printf(", CL%d)", val);
}
/*
* Initialize Local Bus
*/
void
local_bus_init(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
uint temp_lbcdll;
/*
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66Mhz, DLL bypass mode must be used.
* If localbus freq is > 133Mhz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr |= 0x80000000; /* DLL Bypass */
} else if (lbc_hz >= 133) {
lbc->lcrr &= (~0x80000000); /* DLL Enabled */
} else {
lbc->lcrr &= (~0x8000000); /* DLL Enabled */
udelay(200);
/*
* Sample LBC DLL ctrl reg, upshift it to set the
* override bits.
*/
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm("sync;isync;msync");
}
}
