/* System timer */ void init_timer() { int i; for (i = 0; i < MAX_PROCS; i++) { ticks_remaining[i] = 0; } // Setup timer interrupt service routine(ISR) isr_table[TIMER_IRQ] = isr_timer; // Enable receive timer interrupt IRQ enable_irq(TIMER_IRQ); get_system_timer()->C3 = get_system_timer()->CLO + (CLOCK_FREQ / CLKTICKS_PER_SEC); timer_port = create_process(timer_process, 6, 0, "Timer Process"); }
void _sleep(unsigned int millisecond) { u_long time = get_system_timer() + millisecond * 1000; while (get_system_timer() < time) { dummy(time); } int i; for (i = 0; i < 150; i++) { dummy(time); } }
void isr_timer(void) { PROCESS p = interrupt_table[TIMER_IRQ]; if (p != NULL && p->state == STATE_INTR_BLOCKED) { // Add event handler to read queue add_ready_queue(p); } dmb(); // Memory barrier before/after write to peripheral get_system_timer()->CS.M3 = 1; // Clear system timer 3 interrupt /* * set up the new value in the C3 output compare register. This is * done by reading the current low-order bits of the counter and adding the * requested number of cycles. Note that wraparounds will necessarily be * handled correctly because the output compare registers are by design only * 32 bits. */ get_system_timer()->C3 = get_system_timer()->CLO + (CLOCK_FREQ / CLKTICKS_PER_SEC); dmb(); }