void __cpuinit platform_secondary_init(unsigned int cpu)
{
trace_hardirqs_off();
/*
* the primary core may have used a "cross call" soft interrupt
* to get this processor out of WFI in the BootMonitor - make
* sure that we are no longer being sent this soft interrupt
*/
smp_cross_call_done(cpumask_of_cpu(cpu));
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
if (machine_is_realview_eb() && core_tile_eb11mp())
gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
else if (machine_is_realview_pb11mp())
gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
pen_release = -1;
smp_wmb();
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
static void __init gic_init_irq(void)
{
if (core_tile_eb11mp() || core_tile_a9mp()) {
unsigned int pldctrl;
/* new irq mode */
writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
pldctrl |= 0x00800000;
writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
/* core tile GIC, primary */
gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
gic_cpu_init(0, gic_cpu_base_addr);
#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
/* board GIC, secondary */
gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
#endif
} else {
/* board GIC, primary */
gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
gic_cpu_init(0, gic_cpu_base_addr);
}
}
static void __init gic_init_irq(void)
{
/* ARM1176 DevChip GIC, primary */
gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START);
gic_cpu_init(0, gic_cpu_base_addr);
/* board GIC, secondary */
gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START);
gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
}
static void __init gic_init_irq(void)
{
gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START);
gic_cpu_init(0, gic_cpu_base_addr);
gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START);
gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
}
static void __init gic_init_irq(void)
{
if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE);
gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
29);
gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
} else {
gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE);
gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE),
IRQ_PBX_GIC_START);
gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE));
}
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
trace_hardirqs_off();
/*
* the primary core may have used a "cross call" soft interrupt
* to get this processor out of WFI in the BootMonitor - make
* sure that we are no longer being sent this soft interrupt
*/
smp_cross_call_done(cpumask_of_cpu(cpu));
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, gic_cpu_base_addr);
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
pen_release = -1;
smp_wmb();
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
/* Initialization routine for secondary CPUs after they are brought out of
* reset.
*/
void platform_secondary_init(unsigned int cpu)
{
printk(KERN_DEBUG "%s: cpu:%d\n", __func__, cpu);
#ifdef CONFIG_HOTPLUG_CPU
WARN_ON(msm_pm_platform_secondary_init(cpu));
#endif
trace_hardirqs_off();
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
/* RUMI does not adhere to GIC spec by enabling STIs by default.
* Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
*/
if (machine_is_msm8x60_surf() ||
machine_is_msm8x60_ffa() ||
machine_is_msm8x60_rumi3())
writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
/*
* setup GIC (GIC number NOT CPU number and the base address of the
* GIC CPU interface
*/
gic_cpu_init(0, MSM_QGIC_CPU_BASE);
}
void __init tegra_init_irq(void)
{
struct irq_chip *gic;
unsigned int i;
for (i=0; i<PPI_NR; i++) {
writel(~0, ictlr_to_virt(i) + ICTLR_CPU_IER_CLR);
writel(0, ictlr_to_virt(i) + ICTLR_CPU_IEP_CLASS);
}
gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 29);
gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
gic = get_irq_chip(29);
gic_unmask_irq = gic->unmask;
gic_mask_irq = gic->mask;
tegra_irq.ack = gic->ack;
#ifdef CONFIG_SMP
tegra_irq.set_affinity = gic->set_affinity;
#endif
for (i=INT_PRI_BASE; i<INT_SYNCPT_THRESH_BASE; i++) {
set_irq_chip(i, &tegra_irq);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
syncpt_init_irq();
}
static void __init gic_init_irq(void)
{
/* ARM PB-A8 on-board GIC */
gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE);
gic_dist_init(0, __io_address(REALVIEW_PBA8_GIC_DIST_BASE), IRQ_PBA8_GIC_START);
gic_cpu_init(0, __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
}
void __init msm8x60_init_irq(void)
{
unsigned int i;
gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
gic_cpu_init(0, MSM_QGIC_CPU_BASE);
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
/* QGIC does not adhere to GIC spec by enabling STIs by default.
* Enable/clear is supposed to be RO for STIs, but is RW on QGIC.
*/
if (!machine_is_msm8x60_sim())
writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
* as they are configured as level, which does not play nice with
* handle_percpu_irq.
*/
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
set_irq_handler(i, handle_percpu_irq);
}
}
//----------------------------------------------------------------
static
void zynq_irq_init()
{
gic_cpu_base_addr = (void *)(IO_ADDRESS(ZYNQ_GIC_CPU_PHYS_BASE));
gic_dist_init(0, IO_ADDRESS(ZYNQ_GIC_DIST_PHYS_BASE), INT_PPI_2_PTIMER);
gic_cpu_init(0, IO_ADDRESS(ZYNQ_GIC_CPU_PHYS_BASE));
}
static void __init gic_init_irq(void)
{
#ifdef CONFIG_REALVIEW_MPCORE
unsigned int pldctrl;
writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
pldctrl |= 0x00800000; /* New irq mode */
writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
#endif
gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE));
#if defined(CONFIG_REALVIEW_MPCORE) && !defined(CONFIG_REALVIEW_MPCORE_REVB)
gic_dist_init(1, __io_address(REALVIEW_GIC1_DIST_BASE), 64);
gic_cpu_init(1, __io_address(REALVIEW_GIC1_CPU_BASE));
gic_cascade_irq(1, IRQ_EB_IRQ1);
#endif
}
void __init s5pv310_init_irq(void)
{
int irq;
#ifdef CONFIG_USE_EXT_GIC
gic_cpu_base_addr = S5P_VA_EXTGIC_CPU;
gic_dist_init(0, S5P_VA_EXTGIC_DIST, IRQ_SPI(0));
gic_cpu_init(0, S5P_VA_EXTGIC_CPU);
#else
gic_cpu_base_addr = S5P_VA_GIC_CPU;
gic_dist_init(0, S5P_VA_GIC_DIST, IRQ_SPI(0));
gic_cpu_init(0, S5P_VA_GIC_CPU);
#endif
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
#ifdef CONFIG_CPU_S5PV310_EVT1
/* From SPI(0) to SPI(39) and SPI(51), SPI(53)
* are connected to the interrupt combiner. These irqs
* should be initialized to support cascade interrupt.
*/
if ((irq >= 40) && !(irq == 51) && !(irq == 53))
continue;
#endif
#ifdef CONFIG_USE_EXT_GIC
combiner_init(irq, (void __iomem *)S5P_VA_EXTCOMBINER(irq),
COMBINER_IRQ(irq, 0));
#else
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
#endif
combiner_cascade_irq(irq, IRQ_SPI(irq));
}
/* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because S5PV310
* uses GIC instead of VIC.
*/
s5p_init_irq(NULL, 0);
/* Set s3c_irq_wake as set_wake() of GIC irq_chip */
get_irq_chip(IRQ_RTC_ALARM)->set_wake = s3c_irq_wake;
}
static void __init gic_init_irq(void)
{
#ifdef CONFIG_REALVIEW_MPCORE
writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
writel(0x008003c0, __io_address(REALVIEW_SYS_BASE) + 0xd8);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
#endif
gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));
gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
}
void __init ux500_init_irq(void)
{
gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
/*
* Init clocks here so that they are available for system timer
* initialization.
*/
clk_init();
}
/*
* Code to setup the interrupts
*/
static void __init oxnas_init_irq(void)
{
/* initialise the RPS interrupt controller */
OX820_RPS_init_irq(OX820_RPS_IRQ_START, OX820_RPS_IRQ_START + NR_RPS_IRQS);
/* initialise the GIC */
gic_cpu_base_addr = __io_address(OX820_GIC_CPU_BASE_ADDR);
gic_dist_init(0, __io_address(OX820_GIC_DIST_BASE_ADDR), 29);
gic_cpu_init(0, gic_cpu_base_addr);
OX820_RPS_cascade_irq( RPSA_IRQ_INTERRUPT);
}
void __init gic_init_irq(void)
{
/* Static mapping, never released */
gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
BUG_ON(!gic_dist_base_addr);
gic_dist_init(0, gic_dist_base_addr, 29);
/* Static mapping, never released */
gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
BUG_ON(!gic_cpu_base_addr);
gic_cpu_init(0, gic_cpu_base_addr);
}
static void __init gic_init_irq(void)
{
/* irq mode with no DCC */
/* ARM11 MPCore test chip GIC */
gic_cpu_base_addr = (void __iomem *) CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT;
gic_dist_init(0, (void __iomem *) CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, 29);
gic_cpu_init(0, gic_cpu_base_addr);
}
static void __init gic_init_irq(void)
{
#ifdef CONFIG_REALVIEW_MPCORE
unsigned int pldctrl;
writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + 0xd8);
pldctrl |= 0x00800000; /* New irq mode */
writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
#endif
gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));
gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
}
void gic_dev_init(unsigned int nr, int start,
void __iomem *dist_base, void __iomem *cpu_base)
{
struct gic_chip_data *gic;
gic = &gic_data[nr];
gic->dist_base = dist_base;
gic->cpu_base = cpu_base;
#ifndef SKIP_GIC_INIT
gic_dist_init(gic);
gic_cpu_init(gic);
#endif
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
trace_hardirqs_off();
gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
#ifdef CONFIG_HOTPLUG_CPU
cpu_set(cpu, cpu_init_map);
INIT_COMPLETION(per_cpu(cpu_killed, cpu));
#endif
spin_unlock(&boot_lock);
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
trace_hardirqs_off();
/*
* If any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, gic_cpu_base_addr);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
static int __init gic_init_bases(struct vmm_devtree_node *node,
u32 gic_nr,
bool eoimode,
u32 irq_start,
virtual_addr_t cpu_base,
virtual_addr_t cpu2_base,
virtual_addr_t dist_base)
{
u32 max_irqs;
struct gic_chip_data *gic;
BUG_ON(gic_nr >= GIC_MAX_NR);
gic = &gic_data[gic_nr];
gic->eoimode = eoimode;
/* For primary GICs, skip over SGIs.
* For secondary GICs, skip over PPIs, too.
*/
gic->hwirq_base = (gic_nr == 0) ? 16 : 32;
gic->dist_base = dist_base;
gic->cpu_base = cpu_base;
gic->cpu2_base = cpu2_base;
/*
* Find out how many interrupts are supported.
* The GIC only supports up to 1020 interrupt sources.
*/
max_irqs = gic_read(gic->dist_base + GICD_CTR) & 0x1f;
max_irqs = (max_irqs + 1) * 32;
if (max_irqs > 1020)
max_irqs = 1020;
gic->max_irqs = max_irqs;
gic->domain = vmm_host_irqdomain_add(node, (int)irq_start, max_irqs,
&gic_ops, gic);
if (!gic->domain) {
return VMM_EFAIL;
}
gic_dist_init(gic);
gic_cpu_init(gic);
return VMM_OK;
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
trace_hardirqs_off();
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
void platform_secondary_init(unsigned int cpu)
{
printk(KERN_DEBUG "%s: cpu:%d\n", __func__, cpu);
trace_hardirqs_off();
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
if (machine_is_msm8x60_surf() ||
machine_is_msm8x60_ffa() ||
machine_is_msm8x60_rumi3())
writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
gic_cpu_init(0, MSM_QGIC_CPU_BASE);
}
int arm_board_pic_init(void)
{
int rc;
/*
* Initialize Generic Interrupt Controller
*/
rc = gic_dist_init(0, A9_MPCORE_GIC_DIST, IRQ_CA9X4_GIC_START);
if (rc) {
return rc;
}
rc = gic_cpu_init(0, A9_MPCORE_GIC_CPU);
if (rc) {
return rc;
}
return 0;
}
static int __init gic_init_bases(u32 gic_nr,
bool eoimode,
u32 irq_start,
virtual_addr_t cpu_base,
virtual_addr_t cpu2_base,
virtual_addr_t dist_base)
{
u32 max_irqs;
struct gic_chip_data *gic;
BUG_ON(gic_nr >= GIC_MAX_NR);
gic = &gic_data[gic_nr];
gic->eoimode = eoimode;
gic->irq_start = irq_start;
/* For primary GICs, skip over SGIs.
* For secondary GICs, skip over PPIs, too.
*/
gic->hwirq_base = (gic_nr == 0) ? 16 : 32;
gic->dist_base = dist_base;
gic->cpu_base = cpu_base;
gic->cpu2_base = cpu2_base;
/*
* Find out how many interrupts are supported.
* The GIC only supports up to 1020 interrupt sources.
*/
max_irqs = gic_read(gic->dist_base + GIC_DIST_CTR) & 0x1f;
max_irqs = (max_irqs + 1) * 32;
if (max_irqs > 1020)
max_irqs = 1020;
/*
* Limit number of interrupts registered to the platform maximum
*/
BUG_ON((max_irqs + gic->irq_start) > CONFIG_HOST_IRQ_COUNT);
gic->max_irqs = max_irqs;
gic_dist_init(gic);
gic_cpu_init(gic);
return VMM_OK;
}
int __init gic_init(u32 gic_nr, u32 irq_start,
virtual_addr_t cpu_base, virtual_addr_t dist_base)
{
struct gic_chip_data *gic;
if (gic_nr >= GIC_MAX_NR) {
return VMM_EFAIL;
}
gic = &gic_data[gic_nr];
gic->dist_base = dist_base;
gic->cpu_base = cpu_base;
gic->irq_offset = (irq_start - 1) & ~31;
gic_dist_init(gic, irq_start);
gic_cpu_init(gic);
return VMM_OK;
}
void __init s5pv310_init_irq(void)
{
int irq;
gic_cpu_base_addr = S5P_VA_GIC_CPU;
gic_dist_init(0, S5P_VA_GIC_DIST, IRQ_LOCALTIMER);
gic_cpu_init(0, S5P_VA_GIC_CPU);
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
}
/* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because S5PV310
* uses GIC instead of VIC.
*/
s5p_init_irq(NULL, 0);
}
void __init tegra_init_irq(void) {
/*int i;*/
printk("%s\n", __FUNCTION__);
gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 32);
gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
/*for (i=0; i<4; i++) {
__raw_writel(~0UL, ictlr_reg_base[i] + ICTLR_CPU_IER_CLR);
__raw_writel(0, ictlr_reg_base[i] + ICTLR_CPU_IEP_CLASS);
}
for (i=32; i<NR_IRQS; i++) {
if (set_irq_chip(i, &tegra_irq_chip))
BUG();
set_irq_handler(i, handle_level_irq);
}*/
tegra_init_clock();
}