Esempio n. 1
0
/*******************************************************************************
 * Per cpu gic distributor setup which will be done by all cpus after a cold
 * boot/hotplug. This marks out the secure interrupts & enables them.
 ******************************************************************************/
void gic_pcpu_distif_setup(unsigned int gicd_base)
{
    unsigned i;

    /* Mark all 32 PPI interrupts as Group 1 (non-secure) */
    mmio_write_32(gicd_base + GICD_IGROUPR, 0xffffffffu);

    /* Setup PPI priorities doing four at a time */
    for (i = 0; i < 32; i += 4)
        mmio_write_32(gicd_base + GICD_IPRIORITYR + i, DEFAULT_NS_PRIORITY_X4);

    /* Configure those PPIs we want as secure, and enable them. */
    static const char sec_irq[] = {
        IRQ_SEC_PHY_TIMER,
        IRQ_SEC_SGI_0,
        IRQ_SEC_SGI_1,
        IRQ_SEC_SGI_2,
        IRQ_SEC_SGI_3,
        IRQ_SEC_SGI_4,
        IRQ_SEC_SGI_5,
        IRQ_SEC_SGI_6,
        IRQ_SEC_SGI_7
    };
    for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++) {
        gic_set_secure(gicd_base, sec_irq[i]);
        gicd_set_isenabler(gicd_base, sec_irq[i]);
    }
}
/*******************************************************************************
 * Helper function to configure secure G0 SPIs.
 ******************************************************************************/
void gicv2_secure_spis_configure(uintptr_t gicd_base,
				     unsigned int num_ints,
				     const unsigned int *sec_intr_list)
{
	unsigned int index, irq_num;

	/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
	assert(num_ints ? (uintptr_t)sec_intr_list : 1);

	for (index = 0; index < num_ints; index++) {
		irq_num = sec_intr_list[index];
		if (irq_num >= MIN_SPI_ID) {
			/* Configure this interrupt as a secure interrupt */
			gicd_clr_igroupr(gicd_base, irq_num);

			/* Set the priority of this interrupt */
			gicd_write_ipriorityr(gicd_base,
					      irq_num,
					      GIC_HIGHEST_SEC_PRIORITY);

			/* Target the secure interrupts to primary CPU */
			gicd_set_itargetsr(gicd_base, irq_num,
					gicv2_get_cpuif_id(gicd_base));

			/* Enable this interrupt */
			gicd_set_isenabler(gicd_base, irq_num);
		}
	}

}
Esempio n. 3
0
static void tbase_triggerSgiDump(void)
{
  uint64_t mpidr = read_mpidr();
  uint32_t linear_id = platform_get_core_pos(mpidr);

  uint32_t SGITargets;

  /* Configure SGI */
  gicd_clr_igroupr(get_plat_config()->gicd_base, FIQ_SMP_CALL_SGI);
  gicd_set_ipriorityr(get_plat_config()->gicd_base, FIQ_SMP_CALL_SGI, GIC_HIGHEST_SEC_PRIORITY);      

  /* Enable SGI */
  gicd_set_isenabler(get_plat_config()->gicd_base, FIQ_SMP_CALL_SGI);

  /* Send SGIs to all cores except the current one 
     (current will directly branch to the dump handler) */
  SGITargets = 0xFF;
  SGITargets &= ~(1 << linear_id);

  /* Trigger SGI */
  irq_raise_softirq(SGITargets, FIQ_SMP_CALL_SGI);

  /* Current core directly branches to dump handler */
  plat_tbase_dump();
}
Esempio n. 4
0
/*******************************************************************************
 * Global gic distributor setup which will be done by the primary cpu after a
 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
 * then enables the secure GIC distributor interface.
 ******************************************************************************/
static void gic_distif_setup(unsigned int gicd_base)
{
    unsigned int i, ctlr;
    const unsigned int ITLinesNumber =
        gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;

    /* Disable the distributor before going further */
    ctlr = gicd_read_ctlr(gicd_base);
    ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
    gicd_write_ctlr(gicd_base, ctlr);

    /* Mark all lines of SPIs as Group 1 (non-secure) */
    for (i = 0; i < ITLinesNumber; i++)
        mmio_write_32(gicd_base + GICD_IGROUPR + 4 + i * 4, 0xffffffffu);

    /* Setup SPI priorities doing four at a time */
    for (i = 0; i < ITLinesNumber * 32; i += 4)
        mmio_write_32(gicd_base + GICD_IPRIORITYR + 32 + i, DEFAULT_NS_PRIORITY_X4);

    /* Configure the SPIs we want as secure */
    static const char sec_irq[] = {
        IRQ_MHU,
        IRQ_GPU_SMMU_0,
        IRQ_GPU_SMMU_1,
        IRQ_ETR_SMMU,
        IRQ_TZC400,
        IRQ_TZ_WDOG
    };
    for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++)
        gic_set_secure(gicd_base, sec_irq[i]);

    /* Route watchdog interrupt to this CPU and enable it. */
    gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG,
                       platform_get_core_pos(read_mpidr()));
    gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG);

    /* Now setup the PPIs */
    gic_pcpu_distif_setup(gicd_base);

    /* Enable Group 0 (secure) interrupts */
    gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0);
}