static int gpu_set_voltage(struct exynos_context *platform, int vol)
{
if (gpu_get_cur_voltage(platform) == vol)
return 0;
if (!gpu_is_power_on()) {
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't set voltage in the power-off state!\n", __func__);
return -1;
}
#ifdef CONFIG_REGULATOR
if (!g3d_regulator) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: regulator is not initialized\n", __func__);
return -1;
}
#ifdef CONFIG_EXYNOS_CL_DVFS_G3D
regulator_sync_voltage(g3d_regulator);
#endif /* CONFIG_EXYNOS_CL_DVFS_G3D */
if (regulator_set_voltage(g3d_regulator, vol, vol) != 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to set voltage, voltage: %d\n", __func__, vol);
return -1;
}
#endif /* CONFIG_REGULATOR */
platform->cur_voltage = gpu_get_cur_voltage(platform);
GPU_LOG(DVFS_DEBUG, LSI_VOL_VALUE, vol, platform->cur_voltage, "voltage set: %d, voltage get:%d\n", vol, platform->cur_voltage);
return 0;
}
int gpu_enable_dvs(struct exynos_context *platform)
{
#ifdef CONFIG_EXYNOS_CL_DVFS_G3D
int level = 0;
#endif /* CONFIG_EXYNOS_CL_DVFS_G3D */
if (!platform->dvs_status)
return 0;
if (!gpu_is_power_on()) {
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't set dvs in the power-off state!\n", __func__);
return -1;
}
#if defined(CONFIG_REGULATOR_S2MPS15)
#ifdef CONFIG_EXYNOS_CL_DVFS_G3D
level = gpu_dvfs_get_level(gpu_get_cur_clock(platform));
exynos7420_cl_dvfs_stop(ID_G3D, level);
#endif /* CONFIG_EXYNOS_CL_DVFS_G3D */
/* Do not need to enable dvs during suspending */
if (!pkbdev->pm.suspending) {
if (s2m_set_dvs_pin(true) != 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to enable dvs\n", __func__);
return -1;
}
}
#endif /* CONFIG_REGULATOR_S2MPS13 */
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "dvs is enabled (vol: %d)\n", gpu_get_cur_voltage(platform));
return 0;
}
void gpu_power_set_reg(void)
{
__raw_writel(LOCAL_PWR_CFG, EXYNOS_PMU_G3D_CONFIGURATION);
while(1)
{
if(gpu_is_power_on())
break;
}
}
int gpu_register_dump(void)
{
if (gpu_is_power_on()) {
#if 0
/* G3D PMU */
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x105C4064, __raw_readl(EXYNOS5430_G3D_STATUS),
"REG_DUMP: EXYNOS5430_G3D_STATUS %x\n", __raw_readl(EXYNOS5430_G3D_STATUS));
/* G3D PLL */
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0000, __raw_readl(EXYNOS5430_G3D_PLL_LOCK),
"REG_DUMP: EXYNOS5430_G3D_PLL_LOCK %x\n", __raw_readl(EXYNOS5430_G3D_PLL_LOCK));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0100, __raw_readl(EXYNOS5430_G3D_PLL_CON0),
"REG_DUMP: EXYNOS5430_G3D_PLL_CON0 %x\n", __raw_readl(EXYNOS5430_G3D_PLL_CON0));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0104, __raw_readl(EXYNOS5430_G3D_PLL_CON1),
"REG_DUMP: EXYNOS5430_G3D_PLL_CON1 %x\n", __raw_readl(EXYNOS5430_G3D_PLL_CON1));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA010c, __raw_readl(EXYNOS5430_G3D_PLL_FREQ_DET),
"REG_DUMP: EXYNOS5430_G3D_PLL_FREQ_DET %x\n", __raw_readl(EXYNOS5430_G3D_PLL_FREQ_DET));
/* G3D SRC */
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0200, __raw_readl(EXYNOS5430_SRC_SEL_G3D),
"REG_DUMP: EXYNOS5430_SRC_SEL_G3D %x\n", __raw_readl(EXYNOS5430_SRC_SEL_G3D));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0300, __raw_readl(EXYNOS5430_SRC_ENABLE_G3D),
"REG_DUMP: EXYNOS5430_SRC_ENABLE_G3D %x\n", __raw_readl(EXYNOS5430_SRC_ENABLE_G3D));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0400, __raw_readl(EXYNOS5430_SRC_STAT_G3D),
"REG_DUMP: EXYNOS5430_SRC_STAT_G3D %x\n", __raw_readl(EXYNOS5430_SRC_STAT_G3D));
/* G3D DIV */
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0600, __raw_readl(EXYNOS5430_DIV_G3D),
"REG_DUMP: EXYNOS5430_DIV_G3D %x\n", __raw_readl(EXYNOS5430_DIV_G3D));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0604, __raw_readl(EXYNOS5430_DIV_G3D_PLL_FREQ_DET),
"REG_DUMP: EXYNOS5430_DIV_G3D_PLL_FREQ_DET %x\n", __raw_readl(EXYNOS5430_DIV_G3D_PLL_FREQ_DET));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0700, __raw_readl(EXYNOS5430_DIV_STAT_G3D),
"REG_DUMP: EXYNOS5430_DIV_STAT_G3D %x\n", __raw_readl(EXYNOS5430_DIV_STAT_G3D));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0704, __raw_readl(EXYNOS5430_DIV_STAT_G3D_PLL_FREQ_DET),
"REG_DUMP: EXYNOS5430_DIV_STAT_G3D_PLL_FREQ_DET %x\n", __raw_readl(EXYNOS5430_DIV_STAT_G3D_PLL_FREQ_DET));
/* G3D ENABLE */
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0800, __raw_readl(EXYNOS5430_ENABLE_ACLK_G3D),
"REG_DUMP: EXYNOS5430_ENABLE_ACLK_G3D %x\n", __raw_readl(EXYNOS5430_ENABLE_ACLK_G3D));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0900, __raw_readl(EXYNOS5430_ENABLE_PCLK_G3D),
"REG_DUMP: EXYNOS5430_ENABLE_PCLK_G3D %x\n", __raw_readl(EXYNOS5430_ENABLE_PCLK_G3D));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0A00, __raw_readl(EXYNOS5430_ENABLE_SCLK_G3D),
"REG_DUMP: EXYNOS5430_ENABLE_SCLK_G3D %x\n", __raw_readl(EXYNOS5430_ENABLE_SCLK_G3D));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0B00, __raw_readl(EXYNOS5430_ENABLE_IP_G3D0),
"REG_DUMP: EXYNOS5430_ENABLE_IP_G3D0 %x\n", __raw_readl(EXYNOS5430_ENABLE_IP_G3D0));
GPU_LOG(DVFS_DEBUG, LSI_REGISTER_DUMP, 0x14AA0B0A, __raw_readl(EXYNOS5430_ENABLE_IP_G3D1),
"REG_DUMP: EXYNOS5430_ENABLE_IP_G3D1 %x\n", __raw_readl(EXYNOS5430_ENABLE_IP_G3D1));
#endif
}
return 0;
}
static int gpu_clock_off(struct exynos_context *platform)
{
int ret = 0;
if (!platform)
return -ENODEV;
#ifdef CONFIG_PM_RUNTIME
if (platform->exynos_pm_domain)
mutex_lock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_PM_RUNTIME */
#if 0
#ifdef GPU_DYNAMIC_CLK_GATING
gpu_dcg_disable(platform);
#endif /* GPU_DYNAMIC_CLK_GATING */
#endif
if (!gpu_is_power_on()) {
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't set clock off in power off status\n", __func__);
ret = -1;
goto err_return;
}
if (platform->clk_g3d_status == 0) {
ret = 0;
goto err_return;
}
#if 0
if (aclk_g3d) {
(void)clk_disable_unprepare(aclk_g3d);
GPU_LOG(DVFS_DEBUG, LSI_CLOCK_OFF, 0u, 0u, "clock is disabled\n");
}
#endif
platform->clk_g3d_status = 0;
err_return:
#ifdef CONFIG_PM_RUNTIME
if (platform->exynos_pm_domain)
mutex_unlock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_PM_RUNTIME */
return ret;
}
static int gpu_set_maximum_outstanding_req(int val)
{
volatile unsigned int reg;
if (val > 0b1111)
return -1;
if (!pkbdev)
return -2;
if (!gpu_is_power_on())
return -3;
reg = kbase_os_reg_read(pkbdev, GPU_CONTROL_REG(L2_MMU_CONFIG));
reg &= ~(0b1111 << 24);
reg |= ((val & 0b1111) << 24);
kbase_os_reg_write(pkbdev, GPU_CONTROL_REG(L2_MMU_CONFIG), reg);
return 0;
}
static ssize_t show_clock(struct device *dev, struct device_attribute *attr, char *buf)
{
ssize_t ret = 0;
struct exynos_context *platform = (struct exynos_context *)pkbdev->platform_context;
if (!platform)
return -ENODEV;
ret += snprintf(buf+ret, PAGE_SIZE-ret, "%d", gpu_is_power_on() * gpu_get_cur_clock(platform));
if (ret < PAGE_SIZE - 1) {
ret += snprintf(buf+ret, PAGE_SIZE-ret, "\n");
} else {
buf[PAGE_SIZE-2] = '\n';
buf[PAGE_SIZE-1] = '\0';
ret = PAGE_SIZE-1;
}
return ret;
}
int gpu_dcg_enable(struct exynos_context *platform)
{
int *p_dcg;
if (!platform)
return -ENODEV;
if (!gpu_is_power_on()) {
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "%s: can't set clock on in power off status\n", __func__);
return -1;
}
p_dcg = (int *)ioremap_nocache(G3D_NOC_DCG_EN, 4);
/* ACLK_G3DND_600 is the same as the ACLK_G3D, so the current clock is read */
if (platform->cur_clock < 275)
*p_dcg = 0x3;
else
*p_dcg = 0x1;
iounmap(p_dcg);
return 0;
}
static int gpu_set_clock_to_osc(struct exynos_context *platform)
{
int ret = 0;
#ifdef CONFIG_MALI_RT_PM
if (platform->exynos_pm_domain)
mutex_lock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_MALI_RT_PM */
if (!gpu_is_power_on()) {
ret = -1;
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't control clock in the power-off state!\n", __func__);
goto err;
}
if (!gpu_is_clock_on()) {
ret = -1;
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't control clock in the clock-off state!\n", __func__);
goto err;
}
/* change the mux to osc */
ret = clk_set_parent(mout_g3d_pll, fin_pll);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_parent [mout_g3d_pll]\n", __func__);
goto err;
}
GPU_LOG(DVFS_DEBUG, LSI_CLOCK_VALUE, platform->cur_clock, gpu_get_cur_clock(platform),
"clock set to soc: %d (%d)\n", gpu_get_cur_clock(platform), platform->cur_clock);
err:
#ifdef CONFIG_MALI_RT_PM
if (platform->exynos_pm_domain)
mutex_unlock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_MALI_RT_PM */
return ret;
}
static int gpu_clock_on(struct exynos_context *platform)
{
int ret = 0;
if (!platform)
return -ENODEV;
#ifdef CONFIG_MALI_RT_PM
if (platform->exynos_pm_domain)
mutex_lock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_MALI_RT_PM */
if (!gpu_is_power_on()) {
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "%s: can't set clock on in power off status\n", __func__);
ret = -1;
goto err_return;
}
if (platform->clk_g3d_status == 1) {
ret = 0;
goto err_return;
}
if (aclk_g3d) {
(void) clk_prepare_enable(aclk_g3d);
GPU_LOG(DVFS_DEBUG, LSI_CLOCK_ON, 0u, 0u, "clock is enabled\n");
}
platform->clk_g3d_status = 1;
err_return:
#ifdef CONFIG_MALI_RT_PM
if (platform->exynos_pm_domain)
mutex_unlock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_MALI_RT_PM */
return ret;
}
static int gpu_set_clock(struct exynos_context *platform, int clk)
{
long g3d_rate_prev = -1;
unsigned long g3d_rate = clk * MHZ;
int ret = 0;
int level = 0;
if (aclk_g3d == 0)
return -1;
#ifdef CONFIG_MALI_RT_PM
if (platform->exynos_pm_domain)
mutex_lock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_MALI_RT_PM */
if (!gpu_is_power_on()) {
ret = -1;
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't set clock in the power-off state!\n", __func__);
goto err;
}
g3d_rate_prev = clk_get_rate(aclk_g3d);
/* if changed the VPLL rate, set rate for VPLL and wait for lock time */
if (g3d_rate != g3d_rate_prev) {
ret = clk_set_parent(mout_g3d, fin_pll);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_parent [fin_pll]\n", __func__);
goto err;
}
/*change g3d pll*/
ret = clk_set_rate(fout_g3d_pll, g3d_rate);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_rate [fout_g3d_pll]\n", __func__);
goto err;
}
level = gpu_dvfs_get_level(g3d_rate/MHZ);
if (level < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to gpu_dvfs_get_level \n", __func__);
goto err;
}
ret = clk_set_rate(sclk_hpm_g3d, (clk_get_rate(aclk_g3d)/hpm_freq_table[level]));
if(ret < 0)
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_rate [sclk_hpm_g3d]\n", __func__);
ret = clk_set_parent(mout_g3d, fout_g3d_pll);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_parent [fout_g3d_pll]\n", __func__);
goto err;
}
g3d_rate_prev = g3d_rate;
}
platform->cur_clock = gpu_get_cur_clock(platform);
if (platform->cur_clock != clk_get_rate(fout_g3d_pll)/MHZ)
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "clock value is wrong (aclk_g3d: %d, fout_g3d_pll: %d)\n",
platform->cur_clock, (int) clk_get_rate(fout_g3d_pll)/MHZ);
GPU_LOG(DVFS_DEBUG, LSI_CLOCK_VALUE, g3d_rate/MHZ, platform->cur_clock,
"clock set: %ld, clock get: %d\n", g3d_rate/MHZ, platform->cur_clock);
err:
#ifdef CONFIG_MALI_RT_PM
if (platform->exynos_pm_domain)
mutex_unlock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_MALI_RT_PM */
return ret;
}
int gpu_register_dump(void)
{
if (gpu_is_power_on() && !s2m_get_dvs_is_on()) {
/* MCS Value check */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x10051224 , __raw_readl(EXYNOS7420_VA_SYSREG + 0x1224),
"REG_DUMP: G3D_EMA_RF2_UHD_CON %x\n", __raw_readl(EXYNOS7420_VA_SYSREG + 0x1224));
/* G3D PMU */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x105C4100, __raw_readl(EXYNOS_PMU_G3D_CONFIGURATION),
"REG_DUMP: EXYNOS_PMU_G3D_CONFIGURATION %x\n", __raw_readl(EXYNOS_PMU_G3D_CONFIGURATION));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x105C4104, __raw_readl(EXYNOS_PMU_G3D_STATUS),
"REG_DUMP: EXYNOS_PMU_G3D_STATUS %x\n", __raw_readl(EXYNOS_PMU_G3D_STATUS));
/* G3D PLL */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x105C6100, __raw_readl(EXYNOS_PMU_GPU_DVS_CTRL),
"REG_DUMP: EXYNOS_PMU_GPU_DVS_CTRL %x\n", __raw_readl(EXYNOS_PMU_GPU_DVS_CTRL));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x10576104, __raw_readl(EXYNOS_PMU_GPU_DVS_STATUS),
"REG_DUMP: GPU_DVS_STATUS %x\n", __raw_readl(EXYNOS_PMU_GPU_DVS_STATUS));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x10051234, __raw_readl(EXYNOS7420_VA_SYSREG + 0x1234),
"REG_DUMP: G3D_G3DCFG_REG0 %x\n", __raw_readl(EXYNOS7420_VA_SYSREG + 0x1234));
#ifdef CONFIG_EXYNOS_NOC_DEBUGGING
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14A002F0, __raw_readl(g3d0_outstanding_regs + 0x2F0),
"REG_DUMP: read outstanding %x\n", __raw_readl(g3d0_outstanding_regs + 0x2F0));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14A003F0, __raw_readl(g3d0_outstanding_regs + 0x3F0),
"REG_DUMP: write outstanding %x\n", __raw_readl(g3d0_outstanding_regs + 0x3F0));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14A202F0, __raw_readl(g3d1_outstanding_regs + 0x2F0),
"REG_DUMP: read outstanding %x\n", __raw_readl(g3d1_outstanding_regs + 0x2F0));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14A203F0, __raw_readl(g3d1_outstanding_regs + 0x3F0),
"REG_DUMP: write outstanding %x\n", __raw_readl(g3d1_outstanding_regs + 0x3F0));
#endif /* CONFIG_EXYNOS_NOC_DEBUGGING */
/* G3D PLL */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0000, __raw_readl(G3D_LOCK),
"REG_DUMP: EXYNOS7420_G3D_PLL_LOCK %x\n", __raw_readl(G3D_LOCK));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0100, __raw_readl(G3D_CON),
"REG_DUMP: EXYNOS7420_G3D_PLL_CON0 %x\n", __raw_readl(G3D_CON));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0104, __raw_readl(G3D_CON1),
"REG_DUMP: EXYNOS7420_G3D_PLL_CON1 %x\n", __raw_readl(G3D_CON1));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0108, __raw_readl(G3D_CON2),
"REG_DUMP: EXYNOS7420_G3D_PLL_CON2 %x\n", __raw_readl(G3D_CON2));
/* G3D SRC */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0200, __raw_readl(EXYNOS7420_MUX_SEL_G3D),
"REG_DUMP: EXYNOS7420_SRC_SEL_G3D %x\n", __raw_readl(EXYNOS7420_MUX_SEL_G3D));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0300, __raw_readl(EXYNOS7420_MUX_ENABLE_G3D),
"REG_DUMP: EXYNOS7420_SRC_ENABLE_G3D %x\n", __raw_readl(EXYNOS7420_MUX_ENABLE_G3D));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0400, __raw_readl(EXYNOS7420_MUX_STAT_G3D),
"REG_DUMP: EXYNOS7420_SRC_STAT_G3D %x\n", __raw_readl(EXYNOS7420_MUX_STAT_G3D));
/* G3D DIV */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0600, __raw_readl(EXYNOS7420_DIV_G3D),
"REG_DUMP: EXYNOS7420_DIV_G3D %x\n", __raw_readl(EXYNOS7420_DIV_G3D));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0700, __raw_readl(EXYNOS7420_DIV_STAT_G3D),
"REG_DUMP: EXYNOS7420_DIV_STAT_G3D %x\n", __raw_readl(EXYNOS7420_DIV_STAT_G3D));
/* G3D ENABLE */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0B00, __raw_readl(EXYNOS7420_CLK_ENABLE_IP_G3D),
"REG_DUMP: EXYNOS7420_ENABLE_IP_G3D %x\n", __raw_readl(EXYNOS7420_CLK_ENABLE_IP_G3D));
} else {
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "%s: Power Status %d, DVS Status %d\n", __func__, gpu_is_power_on(), s2m_get_dvs_is_on());
}
return 0;
}
static int gpu_set_clock(struct exynos_context *platform, int clk)
{
long g3d_rate_prev = -1;
unsigned long g3d_rate = clk * MHZ;
int ret = 0;
if (aclk_g3d == 0)
return -1;
#ifdef CONFIG_MALI_RT_PM
if (platform->exynos_pm_domain)
mutex_lock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_MALI_RT_PM */
if (!gpu_is_power_on()) {
ret = -1;
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't set clock in the power-off state!\n", __func__);
goto err;
}
if (!gpu_is_clock_on()) {
ret = -1;
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't set clock in the clock-off state! %d\n", __func__, __raw_readl(EXYNOS5430_ENABLE_ACLK_G3D));
goto err;
}
g3d_rate_prev = clk_get_rate(aclk_g3d);
/* if changed the VPLL rate, set rate for VPLL and wait for lock time */
if (g3d_rate != g3d_rate_prev) {
/*change here for future stable clock changing*/
ret = clk_set_parent(mout_g3d_pll, fin_pll);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_parent [mout_g3d_pll]\n", __func__);
goto err;
}
if (g3d_rate_prev != GPU_OSC_CLK)
sec_debug_aux_log(SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE,
"[GPU] %7d <= %7d", g3d_rate / 1000, g3d_rate_prev / 1000);
/*change g3d pll*/
ret = clk_set_rate(fout_g3d_pll, g3d_rate);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_rate [fout_g3d_pll]\n", __func__);
goto err;
}
/*restore parent*/
ret = clk_set_parent(mout_g3d_pll, fout_g3d_pll);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_parent [mout_g3d_pll]\n", __func__);
goto err;
}
}
platform->cur_clock = gpu_get_cur_clock(platform);
if (platform->cur_clock != clk_get_rate(fout_g3d_pll)/MHZ)
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "clock value is wrong (aclk_g3d: %d, fout_g3d_pll: %d)\n",
platform->cur_clock, (int) clk_get_rate(fout_g3d_pll)/MHZ);
if (g3d_rate != g3d_rate_prev)
GPU_LOG(DVFS_DEBUG, LSI_CLOCK_VALUE, g3d_rate/MHZ, platform->cur_clock, "clock set: %d, clock get: %d\n", (int) g3d_rate/MHZ, platform->cur_clock);
err:
#ifdef CONFIG_MALI_RT_PM
if (platform->exynos_pm_domain)
mutex_unlock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_MALI_RT_PM */
return ret;
}
int gpu_control_state_set(struct kbase_device *kbdev, gpu_control_state state, int param)
{
int ret = 0, voltage;
#ifdef CONFIG_MALI_MIDGARD_DVFS
unsigned long flags;
#endif /* CONFIG_MALI_MIDGARD_DVFS */
struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context;
if (!platform)
return -ENODEV;
mutex_lock(&platform->gpu_clock_lock);
switch (state) {
case GPU_CONTROL_CLOCK_ON:
ret = gpu_clock_on(platform);
#ifdef GPU_EARLY_CLK_GATING
break;
case GPU_CONTROL_CLOCK_ON_POST:
#endif /* GPU_EARLY_CLK_GATING*/
#ifdef CONFIG_MALI_MIDGARD_DVFS
if (!kbdev->pm.metrics.timer_active) {
spin_lock_irqsave(&kbdev->pm.metrics.lock, flags);
kbdev->pm.metrics.timer_active = true;
spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags);
#if !defined(SLSI_SUBSTITUTE)
hrtimer_start(&kbdev->pm.metrics.timer, HR_TIMER_DELAY_MSEC(platform->polling_speed), HRTIMER_MODE_REL);
#else
kbdev->pm.metrics.tlist.expires = jiffies + msecs_to_jiffies(platform->polling_speed);
add_timer_on(&kbdev->pm.metrics.tlist, 0);
#endif
}
gpu_dvfs_handler_control(kbdev, GPU_HANDLER_UPDATE_TIME_IN_STATE, 0);
#endif /* CONFIG_MALI_MIDGARD_DVFS */
break;
#ifdef GPU_EARLY_CLK_GATING
case GPU_CONTROL_CLOCK_OFF_POST:
#else
case GPU_CONTROL_CLOCK_OFF:
#endif /* GPU_EARLY_CLK_GATING*/
#ifdef CONFIG_MALI_MIDGARD_DVFS
if (platform->dvfs_status && kbdev->pm.metrics.timer_active) {
spin_lock_irqsave(&kbdev->pm.metrics.lock, flags);
kbdev->pm.metrics.timer_active = false;
spin_unlock_irqrestore(&kbdev->pm.metrics.lock, flags);
#if !defined(SLSI_SUBSTITUTE)
hrtimer_cancel(&kbdev->pm.metrics.timer);
#else
del_timer(&kbdev->pm.metrics.tlist);
#endif
}
gpu_pm_qos_command(platform, GPU_CONTROL_PM_QOS_RESET);
gpu_dvfs_handler_control(kbdev, GPU_HANDLER_UPDATE_TIME_IN_STATE, platform->cur_clock);
#endif /* CONFIG_MALI_MIDGARD_DVFS */
#ifdef GPU_EARLY_CLK_GATING
break;
case GPU_CONTROL_CLOCK_OFF:
#endif /* GPU_EARLY_CLK_GATING*/
ret = gpu_clock_off(platform);
break;
case GPU_CONTROL_CHANGE_CLK_VOL:
ret = gpu_set_clk_vol(kbdev, param, gpu_dvfs_handler_control(kbdev, GPU_HANDLER_DVFS_GET_VOLTAGE, param));
#ifdef CONFIG_MALI_MIDGARD_DVFS
if (ret == 0) {
ret = gpu_dvfs_handler_control(kbdev, GPU_HANDLER_DVFS_GET_LEVEL, platform->cur_clock);
if (ret >= 0) {
spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags);
platform->step = ret;
spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags);
} else {
GPU_LOG(DVFS_ERROR, "Invalid dvfs level returned [%d]\n", GPU_CONTROL_CHANGE_CLK_VOL);
}
}
if (gpu_pm_qos_command(platform, GPU_CONTROL_PM_QOS_SET) < -1)
GPU_LOG(DVFS_ERROR, "failed to set the PM_QOS\n");
#endif /* CONFIG_MALI_MIDGARD_DVFS */
break;
case GPU_CONTROL_PREPARE_ON:
#ifdef CONFIG_MALI_MIDGARD_DVFS
spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags);
if (platform->dvfs_status && platform->wakeup_lock)
platform->cur_clock = MALI_DVFS_START_FREQ;
if (platform->min_lock > 0)
platform->cur_clock = MAX(platform->min_lock, platform->cur_clock);
if (platform->max_lock > 0)
platform->cur_clock = MIN(platform->max_lock, platform->cur_clock);
platform->down_requirement = platform->table[platform->step].stay_count;
spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags);
#endif /* CONFIG_MALI_MIDGARD_DVFS */
break;
case GPU_CONTROL_IS_POWER_ON:
ret = gpu_is_power_on();
break;
case GPU_CONTROL_SET_MARGIN:
voltage = MAX(platform->table[platform->step].voltage + platform->voltage_margin, COLD_MINIMUM_VOL);
gpu_set_voltage(platform, voltage);
GPU_LOG(DVFS_DEBUG, "we set the voltage: %d\n", voltage);
break;
default:
mutex_unlock(&platform->gpu_clock_lock);
return -1;
}
mutex_unlock(&platform->gpu_clock_lock);
return ret;
}
static int gpu_set_clock(struct exynos_context *platform, int clk)
{
long g3d_rate_prev = -1;
unsigned long g3d_rate = clk * MHZ;
int ret = 0;
#if 0
if (aclk_g3d == 0)
return -1;
#endif
#ifdef CONFIG_PM_RUNTIME
if (platform->exynos_pm_domain)
mutex_lock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_PM_RUNTIME */
if (!gpu_is_power_on()) {
ret = -1;
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't set clock in the power-off state!\n", __func__);
goto err;
}
if (!gpu_is_clock_on()) {
ret = -1;
GPU_LOG(DVFS_INFO, DUMMY, 0u, 0u, "%s: can't set clock in the clock-off state!\n", __func__);
goto err;
}
#if 0
g3d_rate_prev = clk_get_rate(fout_g3d_pll);
/* if changed the VPLL rate, set rate for VPLL and wait for lock time */
if (g3d_rate != g3d_rate_prev) {
ret = gpu_set_maximum_outstanding_req(L2CONFIG_MO_1BY8);
if (ret < 0)
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to set MO (%d)\n", __func__, ret);
/*change here for future stable clock changing*/
ret = clk_set_parent(mout_g3d_pll, fin_pll);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_parent [mout_g3d_pll]\n", __func__);
goto err;
}
/*change g3d pll*/
ret = clk_set_rate(fout_g3d_pll, g3d_rate);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_rate [fout_g3d_pll]\n", __func__);
goto err;
}
/*restore parent*/
ret = clk_set_parent(mout_g3d_pll, fout_g3d_pll);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_parent [mout_g3d_pll]\n", __func__);
goto err;
}
#ifdef CONFIG_SOC_EXYNOS5433_REV_0
/*restore parent*/
ret = clk_set_parent(mout_aclk_g3d, aclk_g3d);
if (ret < 0) {
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to clk_set_parent [mout_ack_g3d]\n", __func__);
goto err;
}
#endif /* CONFIG_SOC_EXYNOS5433_REV_0 */
ret = gpu_set_maximum_outstanding_req(L2CONFIG_MO_NO_RESTRICT);
if (ret < 0)
GPU_LOG(DVFS_ERROR, DUMMY, 0u, 0u, "%s: failed to restore MO (%d)\n", __func__, ret);
g3d_rate_prev = g3d_rate;
}
#endif
platform->cur_clock = gpu_get_cur_clock(platform);
GPU_LOG(DVFS_DEBUG, LSI_CLOCK_VALUE, 0u, g3d_rate/MHZ, "clock set: %ld\n", g3d_rate/MHZ);
GPU_LOG(DVFS_DEBUG, LSI_CLOCK_VALUE, 0u, platform->cur_clock, "clock get: %d\n", platform->cur_clock);
err:
#ifdef CONFIG_PM_RUNTIME
if (platform->exynos_pm_domain)
mutex_unlock(&platform->exynos_pm_domain->access_lock);
#endif /* CONFIG_PM_RUNTIME */
return ret;
}