static void rad1o_ui_set_sample_rate(uint32_t sample_rate) { hackrf_ui_setSampleRate(sample_rate); }
bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom) { const uint64_t VCO_FREQ = 800 * 1000 * 1000; /* 800 MHz */ uint32_t MSx_P1,MSx_P2,MSx_P3; uint32_t a, b, c; uint32_t rem; hackrf_ui_setSampleRate(rate_num/2); /* Find best config */ a = (VCO_FREQ * rate_denom) / rate_num; rem = (VCO_FREQ * rate_denom) - (a * rate_num); if (!rem) { /* Integer mode */ b = 0; c = 1; } else { /* Fractional */ uint32_t g = gcd(rem, rate_num); rem /= g; rate_num /= g; if (rate_num < (1<<20)) { /* Perfect match */ b = rem; c = rate_num; } else { /* Approximate */ c = (1<<20) - 1; b = ((uint64_t)c * (uint64_t)rem) / rate_num; g = gcd(b, c); b /= g; c /= g; } } /* Can we enable integer mode ? */ if (a & 0x1 || b) si5351c_set_int_mode(&clock_gen, 0, 0); else si5351c_set_int_mode(&clock_gen, 0, 1); /* Final MS values */ MSx_P1 = 128*a + (128 * b/c) - 512; MSx_P2 = (128*b) % c; MSx_P3 = c; /* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */ si5351c_configure_multisynth(&clock_gen, 0, MSx_P1, MSx_P2, MSx_P3, 1); /* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */ si5351c_configure_multisynth(&clock_gen, 1, 0, 0, 0, 0);//p1 doesn't matter /* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */ si5351c_configure_multisynth(&clock_gen, 2, 0, 0, 0, 0);//p1 doesn't matter return true; }