/*! * Provide the mipi camera power and reset */ void mipi_cam_power_on(void) { #if defined(BOARD_EVB) board_ioexpander_iomux_config(); /*reset of camera sensor, pin 27 */ max7310_set_gpio_output(0, 2, GPIO_LOW_LEVEL); hal_delay_us(1000); max7310_set_gpio_output(0, 2, GPIO_HIGH_LEVEL); /*power supply through pin25 of connector, for cam_pdown, power down and then up */ max7310_set_gpio_output(0, 0, GPIO_LOW_LEVEL); hal_delay_us(1000); max7310_set_gpio_output(0, 0, GPIO_HIGH_LEVEL); // max7310_set_gpio_output(1, 1, GPIO_HIGH_LEVEL); #endif #if defined(BOARD_SABRE_AI) board_ioexpander_iomux_config(); /*power supply through pin25 of connector, direct connected to P3V3_DELAY, controlled by CPU_PER_RST_B */ /*reset of camera sensor, together with the reset button */ max7310_set_gpio_output(0, 2, GPIO_LOW_LEVEL); hal_delay_us(1000); max7310_set_gpio_output(0, 2, GPIO_HIGH_LEVEL); max7310_set_gpio_output(0, 0, GPIO_HIGH_LEVEL); #endif #if defined(BOARD_SMART_DEVICE) /*power supply through pin25 of connector, for cam_pdown */ gpio_set_gpio(GPIO_PORT6, 9); HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_V(SLOW)); gpio_set_direction(GPIO_PORT6, 9, GPIO_GDIR_OUTPUT); gpio_set_level(GPIO_PORT6, 9, GPIO_HIGH_LEVEL); /*reset of camera sensor, pin 27 */ gpio_set_gpio(GPIO_PORT6, 10); HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE_V(SLOW)); gpio_set_direction(GPIO_PORT6, 10, GPIO_GDIR_OUTPUT); gpio_set_level(GPIO_PORT6, 10, GPIO_LOW_LEVEL); hal_delay_us(1000); gpio_set_level(GPIO_PORT6, 10, GPIO_HIGH_LEVEL); #endif }
static int eeprom_putb(cyg_uint8 b) { int i; for (i = 7; i >= 0; i--) { if (b & (1 << i)) DATA_HI(); else DATA_LO(); CLK_HI(); hal_delay_us(5); CLK_LO(); hal_delay_us(5); } HAL_GPIO_OUTPUT_DISABLE(GPIO_EEPROM_SDA); CLK_HI(); hal_delay_us(5); i = (*IXP425_GPINR & (1 << GPIO_EEPROM_SDA)) ? 0 : 1; CLK_LO(); hal_delay_us(5); DATA_HI(); HAL_GPIO_OUTPUT_ENABLE(GPIO_EEPROM_SDA); return i; }
void gpmi_soft_reset(void) { // Reset the GPMI_CTRL0 block. // Prepare for soft-reset by making sure that SFTRST is not currently // asserted. Also clear CLKGATE so we can wait for its assertion below. HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST); // Wait at least a microsecond for SFTRST to deassert. hal_delay_us(DDI_NAND_HAL_GPMI_SOFT_RESET_LATENCY); while (HW_GPMI_CTRL0.B.SFTRST); // Also clear CLKGATE so we can wait for its assertion below. HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE); // Now soft-reset the hardware. HW_GPMI_CTRL0_SET(BM_GPMI_CTRL0_SFTRST); // Poll until clock is in the gated state before subsequently // clearing soft reset and clock gate. while (!HW_GPMI_CTRL0.B.CLKGATE); // bring GPMI_CTRL0 out of reset HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST); // Wait at least a microsecond for SFTRST to deassert. In actuality, we // need to wait 3 GPMI clocks, but this is much easier to implement. hal_delay_us(DDI_NAND_HAL_GPMI_SOFT_RESET_LATENCY); while (HW_GPMI_CTRL0.B.SFTRST); HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE); // Poll until clock is in the NON-gated state before returning. while (HW_GPMI_CTRL0.B.CLKGATE); }
static int wait_link_up(int wait_ms) { uint32_t val, rx_valid, ltssm; int count; count = wait_ms; do { val = HW_PCIE_PL_DEBUG1_RD() & (0x01 << (36 - 32)); //link is debug bit 36 debug 1 start in bit 32 count--; hal_delay_us(3000); pcie_phy_cr_read(HW_PCIE_PHY_RX_ASIC_OUT_ADDR, &rx_valid); ltssm = HW_PCIE_PL_DEBUG0_RD() & 0x3F; /* * If the link up stuck, reset the phy. This is recommonded by IP vendor. */ if ((ltssm == 0x0D) && ((rx_valid & 0x01) == 0)) { pcie_phy_cr_write(HW_PCIE_PHY_RX_OVRD_IN_LO_ADDR, 0x0028); hal_delay_us(3000); pcie_phy_cr_write(HW_PCIE_PHY_RX_OVRD_IN_LO_ADDR, 0x0000); } } while (!val && (count > 0)); if (!val) return -1; return 0; }
int pcie_init(pcie_dm_mode_e dev_mode) { uint32_t val; pcie_gpr_write_field(diag_status_bus_select, 0xb); pcie_gpr_write_field(app_ltssm_enable, 0); // configure constant input signal to the pcie ctrl and phy pcie_gpr_write_field(device_type, dev_mode); pcie_gpr_write_field(los_level, 9); //phy Loss-Of-Signal detection level. process dependent. pcie_gpr_write_field(tx_deemph_gen1, 0); // typical setting for PCIe 1.1 operation - package dependen pcie_gpr_write_field(tx_deemph_gen2_3p5db, 0); // setting for PCI2 2.0 operation with low de-emphasis setting - package dependen pcie_gpr_write_field(tx_deemph_gen2_6db, 20); // typical setting for PCIe 2.0 operation - package dependen pcie_gpr_write_field(tx_swing_full, 127); // For the default 1.0V amplitude - package dependent pcie_gpr_write_field(tx_swing_low, 127); // to support PCIe Mobile Mode if (dev_mode == PCIE_DM_MODE_RC) { if (NULL != pcie_func_pwr_setup) { pcie_func_pwr_setup(1); } if (NULL != pcie_func_clk_setup) { pcie_func_clk_setup(1); } if (NULL != pcie_func_card_pwr_setup) { pcie_func_card_pwr_setup(1); } // wait for the power stable hal_delay_us(1000 * 10); if (NULL != pcie_func_card_ref_clk_setup) { pcie_func_card_ref_clk_setup(1); } if (NULL != pcie_func_card_rst) { pcie_func_card_rst(); } } // enable ref clk of the phy within i.mx6x pcie_gpr_write_field(ref_ssp_en, 1); // wait for a while, then access the controller's registers. hal_delay_us(1000); //start link up pcie_gpr_write_field(app_ltssm_enable, 1); if (0 != wait_link_up(2000)) { printf("Link timeout.\n"); return -1; } //enable master, io, memory val = HW_PCIE_RC_COMMAND_RD(); val |= BM_PCIE_RC_COMMAND_I_O_SPACE_ENABLE | BM_PCIE_RC_COMMAND_MEMORY_SPACE_ENABLE | BM_PCIE_RC_COMMAND_BUS_MASTER_ENABLE; HW_PCIE_RC_COMMAND_WR(val); return 0; }
/* Reset ADP 1650 A low-to-high transition on the EN pin resets all registers to their default values. SMART_DEVICE -- EN pin: GPIO3_20 */ static void ADP1650_reset(void) { int reset_occupy = 1000, reset_delay = 1000; /* SMART_DEVICE: set camera LED_FLASH_EN through GPIO3_20 */ gpio_set_gpio(GPIO_PORT3, 20); gpio_set_direction(GPIO_PORT3, 20, GPIO_GDIR_OUTPUT); gpio_set_level(GPIO_PORT3, 20, GPIO_LOW_LEVEL); hal_delay_us(reset_occupy); gpio_set_level(GPIO_PORT3, 20, GPIO_HIGH_LEVEL); hal_delay_us(reset_delay); }
static void __check_mii(struct saa9730_priv_data *spd) { unsigned long __base = spd->base; cyg_uint32 opmode; #ifdef DEBUG db_printf("__check_mii\n"); #endif // spin till station is not busy while (SAA9730_MDCTL & SAA9730_MDCTL_BUSY) ; // set PHY address = 'STATUS' SAA9730_MDCTL = SAA9730_MDCTL_BUSY | (PHY_ADDRESS << SAA9730_MDCTL_PHY_SHIFT) | PHY_STATUS; // spin till station is not busy while (SAA9730_MDCTL & SAA9730_MDCTL_BUSY) ; hal_delay_us(1000); // check the link status if (SAA9730_MDDATA & PHY_STATUS_LINK_UP) { SAA9730_MDCTL = SAA9730_MDCTL_BUSY | (PHY_ADDRESS << SAA9730_MDCTL_PHY_SHIFT) | PHY_REG31; // spin till station is not busy while (SAA9730_MDCTL & SAA9730_MDCTL_BUSY) ; hal_delay_us(1000); opmode = (SAA9730_MDDATA & PHY_REG31_OPMODE_MSK) >> PHY_REG31_OPMODE_SHIFT; #ifdef DEBUG db_printf("MII mode %d\n", opmode); #endif if ((opmode == OPMODE_10BASET_FULLDUPLEX) || (opmode == OPMODE_100BASEX_FULLDUPLEX)) SAA9730_MACCTL = SAA9730_MACCTL_CONMODE_FORCE_MII | SAA9730_MACCTL_FULLDUP; else SAA9730_MACCTL = SAA9730_MACCTL_CONMODE_FORCE_MII; }
/* Starting another CPUs */ __externC void cyg_hal_cpu_start(HAL_SMP_CPU_TYPE cpu) { if (cyg_hal_smp_cpu_running[cpu] == 1) return; if (cpu == 0) { cyg_hal_smp_cpu_running[cpu] = 1; hal_scu_join_smp(); } else { hal_delay_us(100); /* Flush cache */ HAL_DCACHE_INVALIDATE_ALL(); HAL_ICACHE_INVALIDATE_ALL(); HAL_DCACHE_SYNC(); HAL_ICACHE_SYNC(); zynq_cpu_stop(cpu); cyg_uint32 trampoline_size = (cyg_uint32)&zynq_secondary_trampoline_jump - (cyg_uint32)&zynq_secondary_trampoline; memcpy(0x0, &zynq_secondary_trampoline, trampoline_size); HAL_WRITE_UINT32(0x0 + trampoline_size, (cyg_uint32)&cyg_hal_smp_start_secondary_cpu); zynq_cpu_start(cpu); } }
/*! * reset camera sensor through GPIO on SMD board * */ void sensor_reset(void) { int32_t reset_occupy = 1000, reset_delay = 1000; sensor_standby(0); /* MX6DQ/SDL_SMART_DEVICE: camera reset through GPIO1_17 */ BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE__ALT5); gpio_set_direction(GPIO_PORT1, 17, GPIO_GDIR_OUTPUT); gpio_set_level(GPIO_PORT1, 17, GPIO_LOW_LEVEL); hal_delay_us(reset_occupy); gpio_set_level(GPIO_PORT1, 17, GPIO_HIGH_LEVEL); hal_delay_us(reset_delay); }
static void do_set_npe_mac(int argc, char *argv[]) { bool portnum_set; int portnum, i; char *addr = 0; struct option_info opts[1]; cyg_uint8 mac[6]; init_opts(&opts[0], 'p', true, OPTION_ARG_TYPE_NUM, (void **)&portnum, (bool *)&portnum_set, "port number"); if (!scan_opts(argc, argv, 1, opts, 1, (void *)&addr, OPTION_ARG_TYPE_STR, "MAC address")) { return; } if ((!portnum_set && addr) || (portnum_set && portnum != 0 && portnum != 1)) { diag_printf("Must specify port with \"-p <0|1>\"\n"); return; } if (!portnum_set) { for (i = 0; i < 2; i++) { cyghal_get_npe_esa(i, mac); diag_printf("NPE eth%d mac: %02x:%02x:%02x:%02x:%02x:%02x\n", i, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); } return; } if (!addr) { cyghal_get_npe_esa(portnum, mac); diag_printf("NPE eth%d mac: %02x:%02x:%02x:%02x:%02x:%02x\n", portnum, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); return; } // parse MAC address from user. // acceptable formats are "nn:nn:nn:nn:nn:nn" and "nnnnnnnnnnnn" for (i = 0; i < 6; i++) { if (!_is_hex(addr[0]) || !_is_hex(addr[1])) break; mac[i] = (_from_hex(addr[0]) * 16) + _from_hex(addr[1]); addr += 2; if (*addr == ':') addr++; } if (i != 6 || *addr != '\0') { diag_printf("Malformed MAC address.\n"); return; } for (i = 0; i < 6; i++) { eeprom_write(MAC_EEPROM_OFFSET(portnum) + i, mac[i]); hal_delay_us(100000); } }
/*! * reset MIPI display */ void mipi_display_reset(void) { #ifdef BOARD_EVB /*pin29 of mipi connector for the LCD reset*/ gpio_set_gpio(GPIO_PORT5, 0); HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR( BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE_V(SLOW)); gpio_set_direction(GPIO_PORT5, 0, GPIO_GDIR_OUTPUT); gpio_set_level(GPIO_PORT5, 0, GPIO_LOW_LEVEL); hal_delay_us(1000); gpio_set_level(GPIO_PORT5, 0, GPIO_HIGH_LEVEL); hal_delay_us(1000); #endif #ifdef BOARD_SABRE_AI /*binded with the board reset button*/ #endif #ifdef BOARD_SMART_DEVICE /*pin29 of mipi connector for the LCD reset*/ gpio_set_gpio(GPIO_PORT6, 11); HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR( BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE_V(SLOW)); gpio_set_direction(GPIO_PORT6, 11, GPIO_GDIR_OUTPUT); gpio_set_level(GPIO_PORT6, 11, GPIO_LOW_LEVEL); hal_delay_us(1000); gpio_set_level(GPIO_PORT6, 11, GPIO_HIGH_LEVEL); hal_delay_us(1000); #endif }
//! This test simply blinks the debug LED at a 1 Hz rate. void gpio_led_test(void) { GpioOutput led(LED_PIN); while (true) { led = !led; hal_delay_us(500000); } }
// Wait for BIOS to configure Verde PCI. // Returns true if BIOS done, false if timeout bool cyg_hal_plf_wait_for_bios(void) { int delay = 200; // 20 seconds, tops while (delay-- > 0) { if (*ATU_ATUCMD & CYG_PCI_CFG_COMMAND_MEMORY) return true; hal_delay_us(100000); } return false; }
static cyg_uint8 eeprom_getb(int more) { int i; cyg_uint8 b = 0; HAL_GPIO_OUTPUT_DISABLE(GPIO_EEPROM_SDA); hal_delay_us(5); for (i = 7; i >= 0; i--) { b <<= 1; if (*IXP425_GPINR & (1 << GPIO_EEPROM_SDA)) b |= 1; CLK_HI(); hal_delay_us(5); CLK_LO(); hal_delay_us(5); } HAL_GPIO_OUTPUT_ENABLE(GPIO_EEPROM_SDA); if (more) DATA_LO(); else DATA_HI(); hal_delay_us(5); CLK_HI(); hal_delay_us(5); CLK_LO(); hal_delay_us(5); return b; }
/*! * @return TEST_PASSED or TEST_FAILED */ test_return_t i2c_device_ppl3115_test(void) { #if defined(BOARD_SMART_DEVICE) // USB_OTG_PWR_EN (EIM_D22) writel(ALT5, IOMUXC_SW_MUX_CTL_PAD_EIM_EB3); gpio_set_direction(GPIO_PORT2, 31, GPIO_GDIR_OUTPUT); gpio_set_level(GPIO_PORT2, 31, GPIO_LOW_LEVEL); hal_delay_us(1000); gpio_set_level(GPIO_PORT2, 31, GPIO_HIGH_LEVEL); #endif //TO be confirmed - i2c-base_addr return i2c_device_id_check_ppl3115(I2C3_BASE_ADDR); }
static int32_t at24cx_write(uint32_t addr, uint8_t *buf) { int32_t ret; at24cxx_i2c_req.buffer = buf; at24cxx_i2c_req.reg_addr = addr; ret = i2c_write(&at24cxx_i2c_req); /* the write cycle time of that EEPROM is max 5ms, * so wait for the write to complete. */ hal_delay_us(5000); return ret; }
/*! * I2C init function to control the FM tuner SI476x. */ static void si476x_i2c_init(void) { /* reset the si476x */ board_ioexpander_iomux_config(); max7310_set_gpio_output(0, 3, GPIO_LOW_LEVEL); hal_delay_us(5000); max7310_set_gpio_output(0, 3, GPIO_HIGH_LEVEL); /* I2C initialization */ i2c_init(g_si476x_i2c_device.port, g_si476x_i2c_device.freq); si476x_i2c_req.ctl_addr = g_si476x_i2c_device.port; si476x_i2c_req.dev_addr = g_si476x_i2c_device.address; // the I2C DEVICE address /* this device does not use registers but command passed through data buffer */ si476x_i2c_req.reg_addr_sz = 0; // number of bytes of I2C device register's address }
static void entry0( cyg_addrword_t data ) { int tick; // Scheduler and thus timer interrupts are running by the // time we get here. // Wait for next tick tick = cyg_current_time(); do {} while (cyg_current_time() == tick); tick = cyg_current_time(); // Then mask timer interrupts HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_RTC); // and wait for the time when the next tick should have come // and check it didn't trigger an interrupt hal_delay_us(TICK_DELAY); CYG_TEST_CHECK(cyg_current_time() == tick, "Timer interrupt while masked"); // Now change interrupt level, and make the check again. Changing // level should not affect interrupt mask state. HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_RTC, 8); hal_delay_us(TICK_DELAY); CYG_TEST_CHECK(cyg_current_time() == tick, "Timer interrupt after changing level"); // Finally unmask the interrupt and make sure it results in ticks. HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_RTC); hal_delay_us(TICK_DELAY); CYG_TEST_CHECK(cyg_current_time() != tick, "No timer interrupt after unmask"); CYG_TEST_PASS_FINISH("SH intr0 test end"); }
/*CPU_PER_RST_B low to high*/ void imx_ar8031_reset(void) { #if defined(BOARD_SMART_DEVICE) /* Select ALT5 mode of ENET_CRS-DV for GPIO1_25 - PGMII_NRST */ /* active low output */ gpio_set_direction(GPIO_PORT1, 25, GPIO_GDIR_OUTPUT); gpio_set_level(GPIO_PORT1, 25, GPIO_LOW_LEVEL); hal_delay_us(500); gpio_set_level(GPIO_PORT1, 25, GPIO_HIGH_LEVEL); #elif defined(BOARD_SABRE_AI) && !defined(BOARD_REV_A) /* CPU_PER_RST_B low to high */ // max7310_set_gpio_output(0, 2, GPIO_LOW_LEVEL); // hal_delay_us(1000); // max7310_set_gpio_output(0, 2, GPIO_HIGH_LEVEL); #endif }
static int eeprom_read(int addr, cyg_uint8 *buf, int nbytes) { cyg_uint8 start_byte; int i; start_byte = 0xA0; // write if (addr & (1 << 8)) start_byte |= 2; for (i = 0; i < 10; i++) if (eeprom_start(start_byte)) break; if (i == 10) { diag_printf("eeprom_read: Can't get write start ACK\n"); return 0; } if (!eeprom_putb(addr & 0xff)) { diag_printf("eeprom_read: Can't get address ACK\n"); return 0; } start_byte |= 1; // READ command if (!eeprom_start(start_byte)) { diag_printf("eeprom_read: Can't get read start ACK\n"); return 0; } for (i = 0; i < (nbytes - 1); i++) *buf++ = eeprom_getb(1); *buf++ = eeprom_getb(0); hal_delay_us(5); eeprom_stop(); return nbytes; }
/*! * set camera sensor clock to 24MHz. * */ void sensor_clock_setting(void) { int32_t clock_delay = 1000; /*MX6DQ/SDL_SMART_DEVICE: config clko */ /*config gpio_0 to be clko */ BW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE__ALT0); BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE__FAST); BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__80_OHM); /*select osc_clk 24MHz, CKO1 output drives cko2 clock */ HW_CCM_CCOSR_WR( BF_CCM_CCOSR_CLKO2_EN(1) | BF_CCM_CCOSR_CLKO2_DIV(0) | /*div 1*/ BF_CCM_CCOSR_CLKO2_SEL(0xe) | /*osc_clk*/ BF_CCM_CCOSR_CLKO_SEL(1) | BF_CCM_CCOSR_CLKO1_EN(1) | BF_CCM_CCOSR_CLKO1_DIV(0)); /*div 1*/ hal_delay_us(clock_delay); }
void ipu_capture_streamoff(uint32_t ipu_index) { int timeout = 5000; /*wait for idmac eof and disable csi-->smfc-->idmac */ /* enable idmac channel 0 eof and wait for eof */ ipu_write_field(ipu_index, IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_0, 1); ipu_write_field(ipu_index, IPU_IPU_INT_STAT_1__IDMAC_EOF_0, 1); while (!(ipu_read(ipu_index, IPU_IPU_INT_STAT_1__ADDR) & 0x1)) { hal_delay_us(10); if (timeout <= 0) break; timeout--; } ipu_disable_csi(ipu_index, 0); ipu_disable_smfc(ipu_index); ipu_idmac_channel_enable(ipu_index, CSI_TO_MEM_CH0, 0); }
static void eeprom_stop(void) { int i; hal_delay_us(5); DATA_LO(); hal_delay_us(5); CLK_HI(); hal_delay_us(5); DATA_HI(); hal_delay_us(5); CLK_LO(); hal_delay_us(5); CLK_HI(); hal_delay_us(5); }
cs_status ptp_get_eg_time(cs_port_id_t port, cs_uint64 *eg_time) { cs_callback_context_t context; cs_uint32 eg_cnt = 0; cs_status rt = CS_E_OK; rt = epon_request_onu_ptp_capture_eg_timestamp(context, 0, 0, port, &eg_cnt); if(rt) { PTP_LOG(IROS_LOG_LEVEL_INF, "get eg_time not ready and try again\n"); /* delay 1ms to retry */ hal_delay_us(10); /* delay 10us */ rt = epon_request_onu_ptp_capture_eg_timestamp(context, 0, 0, port, &eg_cnt); } if(CS_E_OK == rt) { PTP_LOG(IROS_LOG_LEVEL_INF, "eg_cnt = 0x%08x\n", eg_cnt); *eg_time = g_sys_time.time + (eg_cnt - g_sys_time.cnt) * EPON_TQ_TIME; *eg_time += g_tx_time_cr; } return rt; }
/*CPU_PER_RST_B low to high*/ void imx_KSZ9021RN_reset(void) { //max7310_set_gpio_output(0, 2, GPIO_LOW_LEVEL); //hal_delay_us(1000000); //max7310_set_gpio_output(0, 2, GPIO_HIGH_LEVEL); #ifdef BOARD_SABRE_LITE // Config gpio3_GPIO[23] to pad EIM_D23(D25) gpio_set_gpio(GPIO_PORT3, 23); HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR( BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS_V(100K_OHM_PU) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE_V(PULL) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE_V(ENABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE_V(DISABLED) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED_V(100MHZ) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE_V(40_OHM) | BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE_V(SLOW)); gpio_set_direction(GPIO3, 23, GPIO_GDIR_OUTPUT); gpio_set_level(GPIO3, 23, GPIO_LOW_LEVEL); hal_delay_us(1000000); // hold in reset for a delay gpio_set_level(GPIO3, 23, GPIO_LOW_HIGH); #endif }
//////////////////////////////////////////////////////////////////////////////// //! @brief GPMI Set And Start Data Sample Delay. //! //! This function sets the NAND Timing register which controls the delay //! in the data read sampling. It then set the delay hardware to be active //! (if needed by hardware) //! //! @param[in] u32DelayCycles Delay count to put to register //! //! @return None //////////////////////////////////////////////////////////////////////////////// void gpmi_set_and_enable_data_sample_delay(uint32_t u32DelayCycles, uint32_t u32GpmiPeriod_ns) { // DLL_ENABLE must be set to zero when setting RDN_DELAY or HALF_PERIOD!!! BW_GPMI_CTRL1_DLL_ENABLE(0); if ((u32DelayCycles == 0) || (u32GpmiPeriod_ns > GPMI_MAX_DLL_PERIOD_NS) ) { // If no delay is desired, or if GPMI clock period is out of supported // range, then don't enable the delay //BW_GPMI_CTRL1_DLL_ENABLE(0); // This is already done several lines up BW_GPMI_CTRL1_RDN_DELAY(0); BW_GPMI_CTRL1_HALF_PERIOD(0); } else { // Set the delay and needed registers to run. GPMI_CTRL1_HALF_PERIOD is // assumed to have already been set properly uint32_t waitTimeNeeded; BW_GPMI_CTRL1_RDN_DELAY(u32DelayCycles); BW_GPMI_CTRL1_DLL_ENABLE(1); // After the GPMI DLL has been enable it is reqiured to wait for // GPMI_WAIT_CYCLES_AFTER_DLL_ENABLE number of GPMI clock cycles before // using the GPMI interface. // calculate out the wait time and convert from nanoSeconds to microSeconds waitTimeNeeded = (u32GpmiPeriod_ns * GPMI_WAIT_CYCLES_AFTER_DLL_ENABLE) / 1000; // wait until the required time for DLL hardware startup has passed. hal_delay_us(waitTimeNeeded); } }
/* * @brief Initialize mipi lcd panel. * * The supported panel is TRULY panel. * */ static void mipi_lcd_init(void) { int val = 0; /* * Enable the extended command set access. * ffh, 83h, 69h in order to enable the access * any value other than that to disable the access */ gen_write_data(HX8369_CMD_SETEXTC | (HX8369_CMD_SETEXTC_PARAM_1 << 8)); gen_write_cmd((HX8369_CMD_SETEXTC_LEN << 8) | MIPI_DSI_GENERIC_LONG_WRITE); hal_delay_us(1000); #if 0 hal_delay_us(2000); gen_write_cmd(0x00000437); // hal_delay_us(1000); val = gen_read_data((HX8369_CMD_GETHXID << 8) | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM); printf("ID is %d\n", val); #endif /* * set the TRULY MIPI panel * choose DPI mode, resolution is 480x800, RGB24 format * set the timings based on IPU output information */ gen_write_data(HX8369_CMD_SETDISP | (HX8369_CMD_SETDISP_1_HALT << 8) | (HX8369_CMD_SETDISP_2_RES_MODE << 16) | (HX8369_CMD_SETDISP_3_BP << 24)); gen_write_data(HX8369_CMD_SETDISP_4_FP | (HX8369_CMD_SETDISP_5_SAP << 8) | (HX8369_CMD_SETDISP_6_GENON << 16) | (HX8369_CMD_SETDISP_7_GENOFF << 24)); gen_write_data(HX8369_CMD_SETDISP_8_RTN | (HX8369_CMD_SETDISP_9_TEI << 8) | (HX8369_CMD_SETDISP_10_TEP_UP << 16) | (HX8369_CMD_SETDISP_11_TEP_LOW << 24)); gen_write_data(HX8369_CMD_SETDISP_12_BP_PE | (HX8369_CMD_SETDISP_13_FP_PE << 8) | (HX8369_CMD_SETDISP_14_RTN_PE << 16) | (HX8369_CMD_SETDISP_15_GON << 24)); gen_write_cmd((HX8369_CMD_SETDISP_LEN << 8) | MIPI_DSI_GENERIC_LONG_WRITE); /* Set display waveform cycle */ gen_write_data(HX8369_CMD_SETCYC | (HX8369_CMD_SETCYC_PARAM_1 << 8)); gen_write_data(HX8369_CMD_SETCYC_PARAM_2); gen_write_cmd((HX8369_CMD_SETCYC_LEN << 8) | MIPI_DSI_GENERIC_LONG_WRITE); /* Set GIP timing output control */ gen_write_data(HX8369_CMD_SETGIP | (HX8369_CMD_SETGIP_PARAM_1 << 8)); gen_write_data(HX8369_CMD_SETGIP_PARAM_2); gen_write_data(HX8369_CMD_SETGIP_PARAM_3); gen_write_data(HX8369_CMD_SETGIP_PARAM_4); gen_write_data(HX8369_CMD_SETGIP_PARAM_5); gen_write_data(HX8369_CMD_SETGIP_PARAM_6); gen_write_data(HX8369_CMD_SETGIP_PARAM_7); gen_write_cmd((HX8369_CMD_SETGIP_LEN << 8) | MIPI_DSI_GENERIC_LONG_WRITE); /* Set the panel power */ gen_write_data(HX8369_CMD_SETPOWER | (HX8369_CMD_SETPOWER_PARAM_1 << 8)); gen_write_data(HX8369_CMD_SETPOWER_PARAM_2); gen_write_data(HX8369_CMD_SETPOWER_PARAM_3); gen_write_data(HX8369_CMD_SETPOWER_PARAM_4); gen_write_data(HX8369_CMD_SETPOWER_PARAM_5); gen_write_cmd((HX8369_CMD_SETPOWER_LEN << 8) | MIPI_DSI_GENERIC_LONG_WRITE); /* Set VCOM voltage. */ gen_write_data(HX8369_CMD_SETVCOM | (HX8369_CMD_SETVCOM_PARAM_1 << 8)); gen_write_cmd((HX8369_CMD_SETVCOM_LEN << 8) | MIPI_DSI_GENERIC_LONG_WRITE); /* Set Panel format: BGR/RGB */ val = HX8369_CMD_SETPANEL | (HX8369_CMD_SETPANEL_PARAM_1 << 8); gen_write_cmd((val << 8) | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM); /* Set gamma curve related setting */ gen_write_data(HX8369_CMD_SETGAMMA | (HX8369_CMD_SETGAMMA_PARAM_1 << 8)); gen_write_data(HX8369_CMD_SETGAMMA_PARAM_2); gen_write_data(HX8369_CMD_SETGAMMA_PARAM_3); gen_write_data(HX8369_CMD_SETGAMMA_PARAM_4); gen_write_data(HX8369_CMD_SETGAMMA_PARAM_5); gen_write_data(HX8369_CMD_SETGAMMA_PARAM_6); gen_write_data(HX8369_CMD_SETGAMMA_PARAM_7); gen_write_data(HX8369_CMD_SETGAMMA_PARAM_8); gen_write_data(HX8369_CMD_SETGAMMA_PARAM_9); gen_write_cmd((HX8369_CMD_SETGAMMA_LEN << 8) | MIPI_DSI_GENERIC_LONG_WRITE); /* Set MIPI: DPHYCMD & DSICMD, data lane number */ gen_write_data(HX8369_CMD_SETMIPI | (HX8369_CMD_SETMIPI_PARAM_1 << 8)); gen_write_data(HX8369_CMD_SETMIPI_PARAM_2); gen_write_data(HX8369_CMD_SETMIPI_PARAM_3 | HX8369_CMD_SETMIPI_ONELANE); gen_write_data(HX8369_CMD_SETMIPI_PARAM_4); gen_write_cmd((HX8369_CMD_SETMIPI_LEN << 8) | MIPI_DSI_GENERIC_LONG_WRITE); /* Set pixel format:24bpp */ val = HX8369_CMD_SETPIXEL_FMT | (HX8369_CMD_SETPIXEL_FMT_24BPP << 8); gen_write_cmd((val << 8) | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM); /* Set column address: 0~479 */ gen_write_data(HX8369_CMD_SETCLUMN_ADDR | (HX8369_CMD_SETCLUMN_ADDR_PARAM_1 << 8)); gen_write_data(HX8369_CMD_SETCLUMN_ADDR_PARAM_2); gen_write_cmd((HX8369_CMD_SETCLUMN_ADDR_LEN << 8) | MIPI_DSI_GENERIC_LONG_WRITE); /* Set page address: 0~799 */ gen_write_data(HX8369_CMD_SETPAGE_ADDR | (HX8369_CMD_SETPAGE_ADDR_PARAM_1 << 8)); gen_write_data(HX8369_CMD_SETPAGE_ADDR_PARAM_2); gen_write_cmd((HX8369_CMD_SETPAGE_ADDR_LEN << 8) | MIPI_DSI_GENERIC_LONG_WRITE); hal_delay_us(500); /* Set display brightness */ val = HX8369_CMD_WRT_DISP_BRIGHT | (HX8369_CMD_WRT_DISP_BRIGHT_PARAM_1 << 8); gen_write_cmd((val << 8) | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM); val = HX8369_CMD_WRT_CABC_CTRL | (HX8369_CMD_WRT_CABC_CTRL_PARAM_1 << 8); gen_write_cmd((val << 8) | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM); hal_delay_us(500); val = HX8369_CMD_WRT_CTRL_DISP | (HX8369_CMD_WRT_CTRL_DISP_PARAM_1 << 8); gen_write_cmd((val << 8) | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM); hal_delay_us(500); /* exit sleep mode and set display on */ gen_write_cmd((MIPI_DCS_EXIT_SLEEP_MODE << 8) | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM); /* To allow time for the supply voltages * and clock circuits to stabilize. */ hal_delay_us(5000); gen_write_cmd((MIPI_DCS_SET_DISPLAY_ON << 8) | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM); }
cs_status epon_request_onu_ptp_capture_eg_timestamp( CS_IN cs_callback_context_t context, CS_IN cs_int32 device_id, CS_IN cs_int32 llidport, CS_IN cs_port_id_t port_id, CS_OUT cs_uint32 *timestamp ) { cs_aal_ptp_status_t pon_status; cs_status rt = CS_E_OK; if(NULL==timestamp){ SDL_MIN_LOG("ERROR PARAM\n"); rt = CS_E_PARAM; goto END; } if(port_id > UNI_PORT_MAX){ rt = CS_E_PARAM; SDL_MIN_LOG("ERROR Port ID\n"); goto END; } if(port_id == CS_PON_PORT_ID){ cs_uint32 i; cs_uint32 ts; rt = aal_ptp_pon_status_get(&pon_status); if(rt){ SDL_MIN_LOG(" aal_ptp_pon_status_get fail!\n"); goto END; } if(!pon_status.valid) { rt = CS_E_ERROR; SDL_MIN_LOG("Timestamp is invalid\n"); goto END; } for(i=0; i<100; i++) { REG_READ(ONU_MAC_PTP_EG_LATCH, ts); } if(ts != pon_status.egress_timer_latch) { SDL_MIN_LOG("the first ts is wrong(0x%08x)\n", pon_status.egress_timer_latch); } /* clear eg sts */ REG_WRITE(ONU_MAC_PTP_EG_STS, 0x1); *timestamp = ts; } else { cs_uint32 i = 0; cs_uint32 ts0, ts1; cs_boolean ge_eg_valid = 0; do { REG_FIELD_READ(GE_PTP_EG_STS, lt_valid, ge_eg_valid); i++; if(i > 1000) { SDL_MAJ_LOG("ge eg is not ready!\n"); return CS_E_ERROR; } } while(!ge_eg_valid); REG_READ(GE_PTP_EG_LATCH, ts0); hal_delay_us(10); REG_READ(GE_PTP_EG_LATCH, ts1); if(ts0 != ts1) { SDL_MAJ_LOG("ge eg latch is changed!\n"); } #if 0 for(i=1; i<100; i++) { ts_tmp = ts; REG_READ(GE_PTP_EG_LATCH, ts); if(ts != ts_tmp) { SDL_MIN_LOG("%d: 0x%08x - 0x%08x\n", i, ts_tmp, ts); } } if(ts != ts_tmp) { hal_delay_us(1); SDL_MIN_LOG("read last time for ge eg latch reg\n"); REG_READ(GE_PTP_EG_LATCH, ts); ts_tmp = ts; REG_READ(GE_PTP_EG_LATCH, ts); if(ts != ts_tmp) { cs_printf("get eg time fail!\n"); rt = CS_E_ERROR; } } #endif /* clear eg sts */ REG_WRITE(GE_PTP_EG_STS, 0x1); for(i=0; i<1000; i++) { REG_FIELD_READ(GE_PTP_EG_STS, lt_valid, ge_eg_valid); if(ge_eg_valid) { SDL_MAJ_LOG("ge_eg_valid is set\n"); return CS_E_ERROR; } } *timestamp = ts1; } END: return rt; }
cs_status serdes_init(void) { cs_status rt = CS_E_OK; cs_status pll_lock_timeout = 100000; cs_boolean pll_locked; cs_uint8 pre_emphasis=0; cs_uint8 swctrl_tx=0; cs_callback_context_t context; serdes_init_t serdes_init_cfg = { 0x00, // txd_sel; 0x01, // swctrl_tx; 0x00, // speed_tx; 0x03, // hsclksel_tx; 0x04, // mode_rx; 0x00, // speed_rx; 0x03, // hsclksel_rx; 0x02, // refclk_uosel_pll; 0x02, // refclk_losel_pll; 0x00, // refclkin_sel_pll; 0x01, // hsclksel_pll; 0x05, // divsel_pll; 0x02, // clkosel_pll; 0x04, // test_pll; 0x01, // srstz_pmc; 0x01, // pdz_pmc; 0x07, // pdz_misc; 0x01, // r_cal_en; 15 , // __wait_10us_0; 0x01, // pmc_start; 200 , // __wait_150us; 0x1f, // pdz_pll; 0x04, // srstz_pll; 150 , // __wait_100us; 0x01, // pll_control_0; 20000, // __wait_10ms; 0x1f, // pdz_rx; 0x1f, // pdz_tx; 15 , // __wait_10us_1; 0x03, // srst_tx; 0x01, // srst_rx; 10 , // __wait_4t; 0x07 // srstz_digital; }; // enable SSP interrupt //REG_FIELD_WRITE(AHB_SSP_IE, sspe, 1); // lower the clock to K-micro serdes, 1Mhz //REG_FIELD_WRITE(AHB_SSP_CLK, counter_load, 6); // enable SPI_IG cs_plat_ssp_serdes_write(context,0,0,0xe0, 0x01); rt = startup_config_read(CFG_ID_SERDES_SWCTRL_TX, 1, &swctrl_tx); if (rt == CS_E_NOT_FOUND){ AAL_MIN_LOG("Read CFG_ID_SERDES_SWCTRL_TX from startup-cfg FAILED\n"); } else if (rt == CS_E_OK) { if(swctrl_tx<4) /*valid var in startup config,Normal var range from 0-3*/ serdes_init_cfg.swctrl_tx=swctrl_tx; } else { cs_halt("Read CFG_ID_SERDES_SWCTRL_TX from startup-cfg FAILED\n"); } rt = startup_config_read(CFG_ID_SERDES_EMP_EN_TX, 1, &pre_emphasis); if (rt == CS_E_NOT_FOUND){ AAL_MIN_LOG("Read CFG_ID_SERDES_EMP_EN_TX from startup-cfg FAILED\n"); } else if (rt == CS_E_OK) { if(pre_emphasis<0x10) /*valid var in startup config,Normal var range from 0-0xF*/ cs_plat_ssp_serdes_write(context,0,0,0x72,pre_emphasis); } else { cs_halt("Read CFG_ID_SERDES_EMP_EN_TX from startup-cfg FAILED\n"); } cs_plat_ssp_serdes_write(context,0,0,0x10, serdes_init_cfg.txd_sel); cs_plat_ssp_serdes_write(context,0,0,0x71, serdes_init_cfg.swctrl_tx); cs_plat_ssp_serdes_write(context,0,0,0x7c, serdes_init_cfg.speed_tx); cs_plat_ssp_serdes_write(context,0,0,0x7d, serdes_init_cfg.hsclksel_tx); cs_plat_ssp_serdes_write(context,0,0,0x95, serdes_init_cfg.mode_rx); cs_plat_ssp_serdes_write(context,0,0,0x98, serdes_init_cfg.speed_rx); cs_plat_ssp_serdes_write(context,0,0,0x9d, serdes_init_cfg.hsclksel_rx); cs_plat_ssp_serdes_write(context,0,0,0xc0, serdes_init_cfg.refclk_uosel_pll); cs_plat_ssp_serdes_write(context,0,0,0xc1, serdes_init_cfg.refclk_losel_pll); cs_plat_ssp_serdes_write(context,0,0,0xc2, serdes_init_cfg.refclkin_sel_pll); cs_plat_ssp_serdes_write(context,0,0,0xc3, serdes_init_cfg.hsclksel_pll); cs_plat_ssp_serdes_write(context,0,0,0xc6, serdes_init_cfg.divsel_pll); cs_plat_ssp_serdes_write(context,0,0,0xc7, serdes_init_cfg.clkosel_pll); cs_plat_ssp_serdes_write(context,0,0,0xcf, serdes_init_cfg.test_pll); // enable SPI_COM cs_plat_ssp_serdes_write(context,0,0,0xe0, 0x02); cs_plat_ssp_serdes_write(context,0,0,0x00, serdes_init_cfg.srstz_pmc); cs_plat_ssp_serdes_write(context,0,0,0x08, serdes_init_cfg.pdz_pmc); cs_plat_ssp_serdes_write(context,0,0,0x09, serdes_init_cfg.pdz_misc); cs_plat_ssp_serdes_write(context,0,0,0x21, serdes_init_cfg.r_cal_en); hal_delay_us(serdes_init_cfg.__wait_10us_0); cs_plat_ssp_serdes_write(context,0,0,0x20, serdes_init_cfg.pmc_start); hal_delay_us(serdes_init_cfg.__wait_150us); // enable SPI_IG cs_plat_ssp_serdes_write(context,0,0,0xe0, 0x01); cs_plat_ssp_serdes_write(context,0,0,0x0a, serdes_init_cfg.pdz_pll); cs_plat_ssp_serdes_write(context,0,0,0x00, serdes_init_cfg.srstz_pll); // wait for PLL lock do { REG_FIELD_READ(GLOBAL_KM_SDS_STS, pll_lock, pll_locked); }while(!pll_locked && (--pll_lock_timeout)); if(!pll_locked) { AAL_MAJ_LOG("PLL lock failed\n"); return CS_E_ERROR; } else AAL_MAJ_LOG("PLL is locked\n"); hal_delay_us(serdes_init_cfg.__wait_100us); cs_plat_ssp_serdes_write(context,0,0,0x60, serdes_init_cfg.pll_control_0); hal_delay_us(serdes_init_cfg.__wait_10ms); cs_plat_ssp_serdes_write(context,0,0,0x09, serdes_init_cfg.pdz_rx); cs_plat_ssp_serdes_write(context,0,0,0x08, serdes_init_cfg.pdz_tx); hal_delay_us(serdes_init_cfg.__wait_10us_1); cs_plat_ssp_serdes_write(context,0,0,0x01, serdes_init_cfg.srst_tx); cs_plat_ssp_serdes_write(context,0,0,0x02, serdes_init_cfg.srst_rx); hal_delay_us(serdes_init_cfg.__wait_4t); cs_plat_ssp_serdes_write(context,0,0,0x00, serdes_init_cfg.srstz_digital); // disble SSP interrupt //REG_FIELD_WRITE(AHB_SSP_IE, sspe, 0); // reset RSTZ_FIFO to serdes REG_FIELD_WRITE(GLOBAL_KM_SDS_CTRL, rstz_fifo, 0); hal_delay_us(10); REG_FIELD_WRITE(GLOBAL_KM_SDS_CTRL, rstz_fifo, 1); // delay 1ms ensure SerDes's stable hal_delay_us(1000); return rt; }
void SoftwareI2CPort::delay(uint32_t us) { hal_delay_us(us); }