Esempio n. 1
0
File: lpc.c Progetto: thehobn/ec
void lpc_pmc_ibf_interrupt(void){
	/* Channel-1 for ACPI usage*/
	/* Channel-2 for Host Command usage , so the argument data had been
	 * put on the share memory firstly*/
	if (NPCX_HIPMST(PM_CHAN_1) & 0x02)
		handle_acpi_write((NPCX_HIPMST(PM_CHAN_1)&0x08) ? 1 : 0);
	else if (NPCX_HIPMST(PM_CHAN_2)&0x02)
		handle_host_write((NPCX_HIPMST(PM_CHAN_2)&0x08) ? 1 : 0);
}
Esempio n. 2
0
/**
 * LPC interrupt handler
 */
void lpc_interrupt(void)
{
	uint32_t mis = LM4_LPC_LPCMIS;
	uint32_t st;

	/* Clear the interrupt bits we're handling */
	LM4_LPC_LPCIC = mis;

#ifdef HAS_TASK_HOSTCMD
	/* Handle ACPI command and data writes */
	st = LM4_LPC_ST(LPC_CH_ACPI);
	if (st & LM4_LPC_ST_FRMH)
		handle_acpi_write(st & LM4_LPC_ST_CMD);

	/* Handle user command writes */
	st = LM4_LPC_ST(LPC_CH_CMD);
	if (st & LM4_LPC_ST_FRMH)
		handle_host_write(st & LM4_LPC_ST_CMD);
#endif

	/*
	 * Handle port 80 writes (CH0MIS1).  Due to crosbug.com/p/12349 the
	 * interrupt status (mis & LM4_LPC_INT_MASK(LPC_CH_PORT80, 2))
	 * apparently gets lost on back-to-back writes to port 80, so check the
	 * FRMH bit in the channel status register to see if a write is
	 * pending.  Loop to handle bursts of back-to-back writes.
	 */
	while (LM4_LPC_ST(LPC_CH_PORT80) & LM4_LPC_ST_FRMH)
		port_80_write(LPC_POOL_PORT80[0]);

#ifdef HAS_TASK_KEYPROTO
	/* Handle keyboard interface writes */
	st = LM4_LPC_ST(LPC_CH_KEYBOARD);
	if (st & LM4_LPC_ST_FRMH)
		keyboard_host_write(LPC_POOL_KEYBOARD[0], st & LM4_LPC_ST_CMD);

	if (mis & LM4_LPC_INT_MASK(LPC_CH_KEYBOARD, 1)) {
		/* Host read data; wake up task to send remaining bytes */
		task_wake(TASK_ID_KEYPROTO);
	}
#endif

#ifdef CONFIG_UART_HOST
	/* Handle COMx */
	if (lpc_comx_has_char()) {
		/* Copy a character to the UART if there's space */
		if (uart_comx_putc_ok())
			uart_comx_putc(lpc_comx_get_char());
	}
#endif

	/* Debugging: print changes to LPC0RESET */
	if (mis & (1 << 31)) {
		if (LM4_LPC_LPCSTS & (1 << 10)) {
			int i;

			/* Store port 80 reset event */
			port_80_write(PORT_80_EVENT_RESET);

			/*
			 * Workaround for crosbug.com/p/12349; clear all FRMH
			 * bits so host writes will trigger interrupts.
			 */
			for (i = 0; i < 8; i++)
				LM4_LPC_ST(i) &= ~LM4_LPC_ST_FRMH;
		}

		CPRINTS("LPC RESET# %sasserted",
			lpc_get_pltrst_asserted() ? "" : "de");
	}
}