void tx_irq_handle(void)
{
unsigned tx_status = aocec_rd_reg(CEC_TX_MSG_STATUS);
switch (tx_status) {
case TX_DONE:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
case TX_BUSY:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
case TX_ERROR:
if (cec_msg_dbg_en == 1)
hdmi_print(INF, CEC "TX ERROR!!!\n");
if (RX_ERROR == aocec_rd_reg(CEC_RX_MSG_STATUS))
cec_hw_reset();
else
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
/* aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP); */
break;
default:
break;
}
hd_write_reg(P_AO_CEC_INTR_CLR,
hd_read_reg(P_AO_CEC_INTR_CLR) | (1 << 1));
/* hd_write_reg(P_AO_CEC_INTR_MASKN, */
/* hd_read_reg(P_AO_CEC_INTR_MASKN) | (1 << 2)); */
}
int cec_ll_rx(unsigned char *msg, unsigned char *len)
{
int i;
int ret = -1;
int pos;
if ((RX_DONE != aocec_rd_reg(CEC_RX_MSG_STATUS)) ||
(1 != aocec_rd_reg(CEC_RX_NUM_MSG))) {
/* cec_rx_buf_check(); */
hd_write_reg(P_AO_CEC_INTR_CLR,
hd_read_reg(P_AO_CEC_INTR_CLR) | (1 << 2));
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
return ret;
}
*len = aocec_rd_reg(CEC_RX_MSG_LENGTH) + 1;
for (i = 0; i < (*len) && i < MAX_MSG; i++)
msg[i] = aocec_rd_reg(CEC_RX_MSG_0_HEADER + i);
ret = aocec_rd_reg(CEC_RX_MSG_STATUS);
hd_write_reg(P_AO_CEC_INTR_CLR,
hd_read_reg(P_AO_CEC_INTR_CLR) | (1 << 2));
if (cec_msg_dbg_en == 1) {
pos = 0;
pos += sprintf(msg_log_buf + pos,
"CEC: rx msg len: %d dat: ", *len);
for (i = 0; i < (*len); i++)
pos += sprintf(msg_log_buf + pos, "%02x ", msg[i]);
pos += sprintf(msg_log_buf + pos, "\n");
msg_log_buf[pos] = '\0';
hdmi_print(INF, CEC "%s", msg_log_buf);
}
/* cec_rx_buf_check(); */
hd_write_reg(P_AO_CEC_INTR_CLR,
hd_read_reg(P_AO_CEC_INTR_CLR) | (1 << 2));
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
return ret;
}
void cec_hw_reset(void)
{
hd_write_reg(P_AO_CEC_GEN_CNTL, 0x1);
/* Enable gated clock (Normal mode). */
hd_set_reg_bits(P_AO_CEC_GEN_CNTL, 1, 1, 1);
/* Release SW reset */
hd_set_reg_bits(P_AO_CEC_GEN_CNTL, 0, 0, 1);
/* Enable all AO_CEC interrupt sources */
if (!cec_int_disable_flag)
hd_set_reg_bits(P_AO_CEC_INTR_MASKN, 0x6, 0, 3);
aocec_wr_reg(CEC_LOGICAL_ADDR0,
(0x1 << 4) | cec_global_info.my_node_index);
/* Cec arbitration 3/5/7 bit time set. */
cec_arbit_bit_time_set(3, 0x118, 0);
cec_arbit_bit_time_set(5, 0x000, 0);
cec_arbit_bit_time_set(7, 0x2aa, 0);
hdmi_print(INF, CEC "hw reset :logical addr:0x%x\n",
aocec_rd_reg(CEC_LOGICAL_ADDR0));
}
static inline void setreg(const struct reg_s *r)
{
hd_write_reg(r->reg, r->val);
/* printk("[0x%x] = 0x%x\n", r->reg, r->val); */
}
