void hi_sata_init(void __iomem * mmio)
{
hi_sata_poweron();
msleep(20);
/* Config SATA clock */
writel(0x1f, REG_BASE_PERI_CTRL + 0x20A8);
msleep(100);
writel(0x1, REG_BASE_PERI_CTRL + 0x20AC);
msleep(100);
/* Config and reset the SATA PHY, SSC enabled */
writel(0x49000679, REG_BASE_SATA + 0xA0);
msleep(100);
writel(0x49000678, REG_BASE_SATA + 0xA0);
msleep(100);
/* Config PHY controller register 1 */
writel(0x345eA4, REG_BASE_SATA + 0x148);
msleep(100);
/* Config PHY controller register 2, and reset SerDes lane */
writel(0x00060552, REG_BASE_SATA + 0x14C);
msleep(100);
writel(0x00020552, REG_BASE_SATA + 0x14C);
msleep(100);
/* Data invert between phy and sata controller */
writel(0x8, REG_BASE_SATA + 0xA4);
msleep(100);
/* Config Spin-up */
writel(0x600000, REG_BASE_SATA + 0x118);
msleep(100);
writel(0x600002, REG_BASE_SATA + 0x118);
msleep(100);
/*
* Config SATA Port phy controller.
* To take effect for 0xF990014C,
* we should force controller to 1.5G mode first
* and then force it to 6G mode.
*/
writel(0xE100000, REG_BASE_SATA + 0x174);
msleep(100);
writel(0xE5A0000, REG_BASE_SATA + 0x174);
msleep(100);
writel(0xE4A0000, REG_BASE_SATA + 0x174);
msleep(1000);
}
void hi_sata_init(void __iomem *mmio)
{
unsigned int tmp;
int i;
hi_sata_poweron();
msleep(20);
hi_sata_clk_open();
hi_sata_phy_clk_sel();
hi_sata_unreset();
msleep(20);
hi_sata_phy_unreset();
msleep(20);
tmp = readl(mmio + HI_SATA_PHY0_CTLH);
tmp |= HI_SATA_DIS_CLK;
writel(tmp, (mmio + HI_SATA_PHY0_CTLH));
tmp = readl(mmio + HI_SATA_PHY1_CTLH);
tmp |= HI_SATA_DIS_CLK;
writel(tmp, (mmio + HI_SATA_PHY1_CTLH));
if (mode_3g) {
tmp = CONFIG_HI_SATA_PHY0_CTLL_3G_VAL;
phy_config = CONFIG_HI_SATA_3G_PHY_CONFIG;
} else {
tmp = CONFIG_HI_SATA_PHY0_CTLL_15G_VAL;
}
writel(tmp, (mmio + HI_SATA_PHY0_CTLL));
writel(CONFIG_HI_SATA_PHYX_CTLH_VAL, (mmio + HI_SATA_PHY0_CTLH));
writel(tmp, (mmio + HI_SATA_PHY1_CTLL));
writel(CONFIG_HI_SATA_PHYX_CTLH_VAL, (mmio + HI_SATA_PHY1_CTLH));
writel(0x84060c15, (mmio + HI_SATA_OOB_CTL));
for (i = 0; i < n_ports; i++)
writel(phy_config, (mmio + 0x100 + i*0x80
+ HI_SATA_PORT_PHYCTL));
hi_sata_phy_reset();
msleep(20);
hi_sata_phy_unreset();
msleep(20);
hi_sata_clk_unreset();
msleep(20);
}
