int nvhost_vic_finalize_poweron(struct platform_device *pdev)
{
struct nvhost_device_data *pdata = nvhost_get_devdata(pdev);
int err;
nvhost_dbg_fn("");
host1x_writel(pdev, flcn_slcg_override_high_a_r(), 0);
host1x_writel(pdev, flcn_cg_r(),
flcn_cg_idle_cg_dly_cnt_f(4) |
flcn_cg_idle_cg_en_f(1) |
flcn_cg_wakeup_dly_cnt_f(4));
err = nvhost_flcn_boot(pdev);
if (err)
return err;
if (pdata->scaling_init) {
err = nvhost_scale_hw_init(pdev);
if (err)
dev_warn(&pdev->dev, "failed to initialize scaling (%d)",
err);
}
return 0;
}
int nvhost_vic03_finalize_poweron(struct platform_device *pdev)
{
host1x_writel(pdev, flcn_slcg_override_high_a_r(), 0);
host1x_writel(pdev, flcn_cg_r(),
flcn_cg_idle_cg_dly_cnt_f(4) |
flcn_cg_idle_cg_en_f(1) |
flcn_cg_wakeup_dly_cnt_f(4));
return vic03_boot(pdev);
}
static int msenc_dma_pa_to_internal_256b(struct platform_device *dev,
u32 offset, u32 internal_offset, bool imem)
{
u32 cmd = msenc_dmatrfcmd_size_256b_f();
u32 pa_offset = msenc_dmatrffboffs_offs_f(offset);
u32 i_offset = msenc_dmatrfmoffs_offs_f(internal_offset);
u32 timeout = 0; /* default*/
if (imem)
cmd |= msenc_dmatrfcmd_imem_true_f();
host1x_writel(dev, msenc_dmatrfmoffs_r(), i_offset);
host1x_writel(dev, msenc_dmatrffboffs_r(), pa_offset);
host1x_writel(dev, msenc_dmatrfcmd_r(), cmd);
return msenc_dma_wait_idle(dev, &timeout);
}
int vi_disable_irq(struct vi *tegra_vi)
{
int val;
int err = 0;
err = nvhost_module_busy(tegra_vi->ndev);
if (err)
return err;
if (tegra_vi->ndev->id) {
/* Disable FIFO Overflow Interrupt */
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_B_INTERRUPT_MASK_0,
0);
/* Reset status register */
val = host1x_readl(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_B_STATUS_0);
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_B_STATUS_0,
val);
} else {
/* interrupts are associated only with master dev vi.0 */
disable_irq(tegra_vi->vi_irq);
/* Disable FIFO Overflow Interrupt */
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_A_INTERRUPT_MASK_0,
0);
/* Reset status register */
val = host1x_readl(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_A_STATUS_0);
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_A_STATUS_0,
val);
}
nvhost_module_idle(tegra_vi->ndev);
return 0;
}
static int vic03_flcn_dma_pa_to_internal_256b(struct platform_device *pdev,
phys_addr_t pa,
u32 internal_offset,
bool imem)
{
u32 cmd = flcn_dmatrfcmd_size_256b_f();
u32 pa_offset = flcn_dmatrffboffs_offs_f(pa);
u32 i_offset = flcn_dmatrfmoffs_offs_f(internal_offset);
u32 timeout = 0; /* default*/
if (imem)
cmd |= flcn_dmatrfcmd_imem_true_f();
host1x_writel(pdev, flcn_dmatrfmoffs_r(), i_offset);
host1x_writel(pdev, flcn_dmatrffboffs_r(), pa_offset);
host1x_writel(pdev, flcn_dmatrfcmd_r(), cmd);
return vic03_flcn_dma_wait_idle(pdev, &timeout);
}
static irqreturn_t vi_isr(int irq, void *dev_id)
{
struct vi *tegra_vi = (struct vi *)dev_id;
int val;
dev_dbg(&tegra_vi->ndev->dev, "%s: ++", __func__);
if (tegra_vi->ndev->id) {
val = host1x_readl(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_B_STATUS_0);
/* changes required as per t124 register spec */
if (val & PPB_FIFO_OVRF)
atomic_inc(&(tegra_vi->vi_out.overflow));
/* Reset interrupt status register */
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_B_STATUS_0,
val);
} else {
val = host1x_readl(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_A_STATUS_0);
/* changes required as per t124 register spec */
if (val & PPA_FIFO_OVRF)
atomic_inc(&(tegra_vi->vi_out.overflow));
/* Reset interrupt status register */
host1x_writel(tegra_vi->ndev,
CSI_CSI_PIXEL_PARSER_A_STATUS_0,
val);
}
schedule_work(&tegra_vi->stats_work);
return IRQ_HANDLED;
}
int msenc_boot(struct platform_device *dev)
{
u32 timeout;
u32 offset;
int err = 0;
struct msenc *m = get_msenc(dev);
/* check if firmware is loaded or not */
if (!m || !m->valid)
return -ENOMEDIUM;
host1x_writel(dev, msenc_dmactl_r(), 0);
host1x_writel(dev, msenc_dmatrfbase_r(),
(m->phys + m->os.bin_data_offset) >> 8);
for (offset = 0; offset < m->os.data_size; offset += 256)
msenc_dma_pa_to_internal_256b(dev,
m->os.data_offset + offset,
offset, false);
msenc_dma_pa_to_internal_256b(dev, m->os.code_offset, 0, true);
/* setup msenc interrupts and enable interface */
host1x_writel(dev, msenc_irqmset_r(),
(msenc_irqmset_ext_f(0xff) |
msenc_irqmset_swgen1_set_f() |
msenc_irqmset_swgen0_set_f() |
msenc_irqmset_exterr_set_f() |
msenc_irqmset_halt_set_f() |
msenc_irqmset_wdtmr_set_f()));
host1x_writel(dev, msenc_irqdest_r(),
(msenc_irqdest_host_ext_f(0xff) |
msenc_irqdest_host_swgen1_host_f() |
msenc_irqdest_host_swgen0_host_f() |
msenc_irqdest_host_exterr_host_f() |
msenc_irqdest_host_halt_host_f()));
host1x_writel(dev, msenc_itfen_r(),
(msenc_itfen_mthden_enable_f() |
msenc_itfen_ctxen_enable_f()));
/* boot msenc */
host1x_writel(dev, msenc_bootvec_r(), msenc_bootvec_vec_f(0));
host1x_writel(dev, msenc_cpuctl_r(),
msenc_cpuctl_startcpu_true_f());
timeout = 0; /* default */
err = msenc_wait_idle(dev, &timeout);
if (err != 0) {
dev_err(&dev->dev, "boot failed due to timeout");
return err;
}
return 0;
}
static int vic03_boot(struct platform_device *pdev)
{
struct vic03 *v = get_vic03(pdev);
u32 timeout;
u32 offset;
int err = 0;
/* check if firmware is loaded or not */
if (!v || !v->ucode.valid)
return -ENOMEDIUM;
if (v->is_booted)
return 0;
err = vic03_wait_mem_scrubbing(pdev);
if (err)
return err;
host1x_writel(pdev, flcn_dmactl_r(), 0);
host1x_writel(pdev, flcn_dmatrfbase_r(),
(v->ucode.dma_addr + v->ucode.os.bin_data_offset) >> 8);
for (offset = 0; offset < v->ucode.os.data_size; offset += 256)
vic03_flcn_dma_pa_to_internal_256b(pdev,
v->ucode.os.data_offset + offset,
offset, false);
vic03_flcn_dma_pa_to_internal_256b(pdev, v->ucode.os.code_offset,
0, true);
/* setup falcon interrupts and enable interface */
host1x_writel(pdev, flcn_irqmset_r(), (flcn_irqmset_ext_f(0xff) |
flcn_irqmset_swgen1_set_f() |
flcn_irqmset_swgen0_set_f() |
flcn_irqmset_exterr_set_f() |
flcn_irqmset_halt_set_f() |
flcn_irqmset_wdtmr_set_f()));
host1x_writel(pdev, flcn_irqdest_r(), (flcn_irqdest_host_ext_f(0xff) |
flcn_irqdest_host_swgen1_host_f() |
flcn_irqdest_host_swgen0_host_f() |
flcn_irqdest_host_exterr_host_f() |
flcn_irqdest_host_halt_host_f()));
host1x_writel(pdev, flcn_itfen_r(), (flcn_itfen_mthden_enable_f() |
flcn_itfen_ctxen_enable_f()));
/* boot falcon */
host1x_writel(pdev, flcn_bootvec_r(), flcn_bootvec_vec_f(0));
host1x_writel(pdev, flcn_cpuctl_r(), flcn_cpuctl_startcpu_true_f());
timeout = 0; /* default */
err = vic03_flcn_wait_idle(pdev, &timeout);
if (err != 0) {
dev_err(&pdev->dev, "boot failed due to timeout");
return err;
}
v->is_booted = true;
return 0;
}
